面向E级计算的高效能片上光交换单元

To satisfy the requirements of future Exascale computing applications, how to efficiently interconnect the processing cores in a many-core/kilo-core processor becomes one of the main challenges in continuously increasing the performance of computing systems. This project focuses on the issues faced by the on-chip interconnects in the aspects of communication bandwidth, energy efficiency, and reliability. To address these issues, a high-performance on-chip optical switch is designed in this project. i) Inspired from multiple multiplexing technologies of the optical signal and the resonant property of Microring Resonators (MRs), a basic optical switch module is designed by utilizing both Wavelength Division Multiplexing (WDM) and Mode Division Multiplexing (MDM) technologies. On this basis, an analysis model of the switching performance is established and worked on. ii) An optical signal loss model is proposed to analyze the relationship between the physical design parameters and the signal loss of basic on-chip optical devices. Then, a reliability model is established to analyze the communication reliability of the designed basic optical switch module. Based on the reliability model, a reliable basic optical switch module is designed by optimizing the key physical parameters. iii) By employing the designed basic optical switch module, the design method of scalability with modularization is researched on and proposed. Then, an on-chip optical switch is designed, which is able to provide high switching capacity, high reliability, modularization, high scalability, and low blocking possibility. In addition, a highly-dynamic configuration mechanism is proposed correspondingly. iv) A comprehensive simulation platform is established at the levels of both device and network, to simulate, validate and analyze the whole design. This project is expected to provide fundamental technical supports for the on-chip optical switching with high performance, and for the implementation of on-chip optical interconnects in a many-core/kilo-core processor for the future Exascale computing.

面向未来E级计算（每秒百亿亿次浮点运算）的应用需求，如何实现众核/千核处理器芯片的高效片上互连，是继续提升系统计算能力的主要挑战之一。本项目针对片上互连在带宽、能效、可靠性等方面所面临的问题，设计高效能的片上光交换单元。主要研究包括：１）从光信号的复用技术与微环谐振器的谐振特性出发，设计融合波分复用技术与模分复用技术的基本光交换模块，并搭建其性能分析模型；２）搭建基本光器件物理参数与损耗之间的损耗模型，进而搭建可靠性模型；基于所搭建的可靠性模型，通过对关键参数的优化，设计高可靠性的基本光交换模块；３）基于基本光交换模块，研究模块化的扩展方式，设计大容量、高可靠性、模块化、易扩展、低阻塞的片上光交换单元以及对应的高效动态配置机制；4）搭建器件级和网络级的综合仿真平台，进行仿真验证与分析。本项目为实现高效能的片上光交换以及未来E级计算中众核/千核处理器的片上光互连提供重要的技术支撑。

片上光互连是面向E级计算的众核/千核处理器芯片的一种高效互连方式，有助于提升系统的计算能力。针对片上互连在带宽、能效、可靠性等方面所面临的问题，本项目研究并设计了高效能的片上光交换单元。主要研究内容及成果包括：.（1）项目组研究了高性能计算系统以及E级计算系统的架构，研究了提高片上互连与交换的性能的技术，也研究了如何分析所设计基本光交换模块的性能；项目组设计了融合波分复用技术与模分复用技术的基本光交换模块，并搭建了其性能分析模型；所设计的基本光交换模块的数据速率随着模式复用数目m的增加而增加，相比现有的基本光交换模块仅为单模式，单端口速率可以提高m倍。.（2）项目组研究了基本光器件的底层物理参数与损耗之间的关系；基于损耗模型，项目组搭建了可靠性模型；在此基础上，项目组提出了可靠性感知的设计机制，可以对关键参数进行探索与优化，设计高可靠性的基本光交换模块。.（3）项目组研究了如何构建片上光交换单元，并对可构成的光片上网络架构进行了研究；基于基本的光交换模块，项目组设计了大容量、高可靠性、模块化、易扩展、低阻塞的片上光交换单元以及对应的配置机制，该设计可以提高单端口数据速率，满足互连、交换中Tbps级别的单链路带宽需求。.（4）项目组研究了如何搭建片上光交换单元的仿真系统；基于器件级的损耗模型，项目组搭建了路由器级、网络级的可视化的仿真平台，实现了基于可靠性模型的综合仿真平台，可以对设计进行不同层级的仿真验证与分析；此外，基于仿真平台，项目组拓展性地提出了构建片上光互连分析的图形化方法，该方法可进一步拓展到其他领域。.（5）项目组还对片上光互连的波长分配、路由算法、应用映射等方面进行了研究，设计了基于所研究模型的波长分配方案、路由算法、应用映射方法和设计机制，进一步扩展了可靠性感知的片上光互连的研究和应用领域。.