片式正温度系数（PTC）陶瓷的细晶调控及导电机理研究

The multilayer chip Positive Temperature Coefficient (PTC) semiconductor ceramic based on co-firing of the Ni-electrode is suitable for the integrated and chip-based trend of electronic components , which requires to massively reduce the size of the PTC ceramics while their electrical properties are substantially increased. It is well known that the electrical performance of the multilayer chip PTC semiconductor ceramic mainly comes from the surface potential barrier of the grain boundary, and decreasing the grain size of the PTC semiconductor ceramic is an effective way to increase the number of grain boundaries. In the project, the combination of a variety of ways to achieve the goal of making the fine grain control of the PTC ceramics had been adopted, such as using nano-powders as raw material, the introduction of Sr2+ for the A-bit, high donor-doped of Y3+, high presintering temperature and low sintering temperature and the method of organic cast relatively to improve the solids extension, meanwhile this project aimed at studying the preparation technology of the PTC ceramics and the physical mechanism of the fine grain and the modification mechanism of the multiple high donor-doped as well as the dynamics mechanism of ceramic's grain growth.Through the grain surface effect to build the many shell distribution theory,in order to study the relationship between the physical mechanism of the grain size effect and conductivity as well as the limitation of fine grain size of the chip PTC ceramics.Besides, through Gaussian distribution model of grain boundary potential barrier to study the transport mechanism of the ceramic's conductivity, the project will preferably support the fine grain control mechanism and the conductivity mechanism both in theory and experiment foundation.

共烧Ni内电极的多层片式正温度系数（PTC）半导瓷适合于电子元器件的集成化和贴片式趋势，而尺寸大规模减小下PTC陶瓷的电学性能反而要大幅提升。多层片式PTC半导瓷的电学性能主要来源于晶界表面势垒，减小PTC半导瓷的晶粒尺寸是增加晶界数目有效途径。本项目拟采用高能球磨的纳米粉体为原料、BaTiO3的Ba位(即A位)引入Sr2+、高施主掺Y3+、高预烧低烧结、相对提高流延浆料固含量的有机流延等多种途径的组合运用实现片式PTC陶瓷的细晶调控，研究片式PTC陶瓷的制备工艺与晶粒细化的机理、多元高施主掺杂改性机理以及陶瓷晶粒生长的动力学机理，通过晶粒的表面效应构建多壳层分布模型，研究细晶后片式PTC陶瓷晶粒尺寸效应与介电、相变等电学性能关系的物理机理及细晶晶粒尺寸极限的物理机理，通过晶界势垒的高斯分布模型研究陶瓷导电的电输运机理，项目将为片式PTC陶瓷的细晶调控及导电机理研究提供理论和实验基础。

多层片式PTCR的研究适合于当前电子元器件集成化与贴片式需求，其在集成电路过流过压保护、马达启动等多领域具有广阔的应用前景。本项目针对多层片式PTC陶瓷关键技术，系统解决了片式PTC陶瓷的细晶调控机理，探索了尺寸效应带来片式PTC陶瓷电学性能改变的根源。申请人对片式PTC陶瓷的研究为本项目积累了一定实验基础，项目执行近3年来，尺寸效应与陶瓷电学性能的理论研究也为本项目的顺利完成奠定了一定的理论基础。本项目采用了A位引入Sr、高施主掺杂Y、高预烧温度低烧结温度的烧结机制、用高能球磨的纳米粉体为原料、合理控制PTC流延生坯的固含量及密度等组合方法的运用来实现片式PTC陶瓷的细晶调控，以及研究晶粒尺寸效应与陶瓷介电特性、相变特性及电导特性的关系，通过这些技术线路的运用解决了片式PTC陶瓷中关键基础性的科学问题，探索了片式PTC半导瓷细晶调控机理及其与陶瓷电学性能的关系。. 通过本项目的实施，得到了晶粒尺寸为0.5-1.5µm，室温电阻率小于50 Ω•cm，升阻比达到5个数量级，相对密度为90%左右的片式细晶PTC陶瓷；掌握了实现细晶制备的高预烧低烧结、多元高施主的机理，推导出烧结动力学方程及导电机理方程，实现了项目指标，完成了项目任务。