处理器的指令级自测试方法

With the further development of our native high-end general chips, it becomes a great challenge to test them effectively, and the high-end chips require the advanced test technology. Software-Based Self-Testing (SBST) has been a promising test method that on-line tests chips just through executing normal programs, and it has achieved satisfying fault coverage on many simple processors. This project proposes SBST methods for the high-end processors targeting both stuck-at faults and delay faults: 1. research SBST on superscalar out-of-order execution processors; 2. research SBST on network-on-chip (NOC); 3. research SBST for delay faults. Through the project, we will propose a BMC-leading SBST that can achieve satisfying fault coverage on superscalar out-of-order execution processors; design concurrent SBST that can prepare test programs with low overhead for NOC, and support dynamic reconfiguration for the new architecture; develop SBST with satisfying fault coverage for delay faults, and with the self-heating way test computer systems under high temperature; finally publish three high-quality papers indexed by SCI. In conclusion, the project will not only degrade the dependence of processor test on the high-speed test devices and reduce the chip cost, but also provide an in-field test with satisfying fault coverage and guarantee the reliability of the computer systems.

随着我国高端通用芯片的长足发展，有效检测它们面临严峻挑战，高端芯片需要先进的测试技术。指令级自测试是一种通过运行正常程序、在线检测芯片的新型测试方法，在简单处理器上已达到了高故障覆盖率。本项目围绕高端处理器固定型故障和时延故障开展指令级自测试方法研究：1、研究超标量乱序执行处理器的指令级自测试方法；2、研究片上网络的指令级自测试方法；3、研究时延故障的指令级自测试方法。通过本项目的研究，课题组拟提出有界模型检验引导的指令级自测试方法，在超标量乱序执行处理器上达到高故障覆盖率；研究并行的指令级自测试方法，为片上网络提供低开销的自测试程序，支持新架构的动态重配置；提出高覆盖率的时延故障指令级自测试方法，以内升温方式检测计算机系统高温下是否稳定工作。本项目不仅有望降低处理器测试对高速测试仪的依赖，节省芯片成本，而且将提供一种高故障覆盖率的现场测试方法。

本项目围绕高端处理器固定型故障和时延故障开展指令级自测试方法研究：1、研究超标量乱序执行处理器的指令级自测试方法；2、研究片上网络的指令级自测试方法；3、研究时延故障的指令级自测试方法。通过本项目的研究，课题组已经提出有界模型检验引导的指令级自测试方法，它在超标量乱序执行处理器的核心模块上达到高故障覆盖率，本项研究成果已经应用到国产自主知识产权处理器龙芯上，使得国产处理器能够进行现场测试；研制了并行的指令级自测试方法，在片上网络上达到了极高的故障覆盖率，有效地支持众核系统的动态重配置，将应用到国防科大自主研发用于超级计算的众核芯片上；提出了高覆盖率的时延故障指令级自测试方法，以内升温方式测试芯片高温条件下的可靠性，将应用到航天研究院的宇航芯片测试过程中。