纳米CMOS工艺超低功耗SRAM和抗辐射SRAM设计关键技术研究

Integrated circuits (ICs), as the strategic high-tech, embody national core competitiveness, extremely ultra-low-power and radiation-hardened ICs are closely related to the national core security. With the technologies shrink to 65nm and 40nm, according to the reports of International Solid State Circuits Conference (ISSCC) and International Nuclear and Space Radiation Effects Conference (NSREC) in 2014, ultra-low-power SRAM and radiation-hardened SRAM are confronted with many design difficulties, many key design techniques need to be resolved. Based on ISSCC and NSREC latest technique trends, this subject will discuss these topics: 1) based on the in-depth study of the failure mechanisms of ultra-low-power SRAM in extreme process corner, very-low voltage and very-high temperature, the high reliability design techniques are proposed, the key circuit structures of SRAM are innovated, and SRAM within stable and reliable work in VDDmin below 400mV and wide temperature range is designed; 2) based on the further study of the effects of well isolation structure, well contact structure, data storage model and single particle type on the radiation mechanism of multiple cell upset, the radiation hardened techniques are proposed, the key circuit structures of radiation hardened SRAM are innovated, and the realization of SRAM in 15MeV.cm2/mg particle radiation is immune for soft error. Related research is expected to obtain a plurality of original research results and has important significance for improving our core IC design capability.

集成电路是体现国家核心竞争力的战略高科技，而超低功耗和抗辐射集成电路更是与国家核心安全息息相关。根据2014年国际固态电路会议（ISSCC）和核与空间辐射效应会议（NSREC）相关报告，随着工艺缩减到65nm和40nm，超低功耗SRAM和抗辐射SRAM设计面临诸多难题，诸多关键技术亟待攻克。本课题正是基于ISSCC和NSREC最新技术趋势：1）深入研究超低功耗SRAM在极端工艺拐角、超低电压和极高温度下的失效机理及高可靠设计技术，创新各关键电路结构，实现SRAM在VDDmin低于400mV下宽温范围内稳定可靠运行；2）深入研究抗辐射SRAM阱隔离结构、阱接触结构、数据存储模式和辐射粒子种类等对单粒子多单元翻转的影响机理及加固设计技术，创新各关键电路结构，实现SRAM在15MeV.cm2/mg粒子辐射下翻转免疫。相关研究有望取得多个原创性研究成果，对提升我国核心集成电路设计水平具有重要意义。

集成电路是体现国家核心竞争力的战略高科技，而超低功耗抗辐射集成电路更是与国家核心安全息息相关。SRAM是CPU、DSP和SoC等集成电路的核心部件，更是单粒子辐射最敏感部件，攻克SRAM低功耗和抗辐射设计关键技术，将SRAM翻转阈值提升到15MeV.cm2/mg以上，对于我国空间用抗辐射集成电路的设计具有重要意义。.本课题：1）深入研究并改进了SRAM的存储单元和外围读写电路，在宽温宽压范围内实现了SRAM的低功耗设计；2）深入研究并量化表征了65nm CMOS工艺下组合逻辑电路中多SET和SET Quenching效应，为SRAM外围读写电路的SET加固设计提供了理论支撑；3）深入研究并量化表征了65nm CMOS工艺下SRAM存储阵列阱隔离结构、阱接触结构、数据存储模式和辐射粒子种类等对单粒子多单元翻转的影响，为SRAM存储阵列的SEU加固提供了理论支撑；4）在65nm CMOS工艺下定制设计了抗辐射SRAM，并研制了单双端口抗辐射SRAM和RF编译器，生成的SRAM在结合EDAC技术的情况下能够在37MeV.cm2/mg实现单粒子翻转免疫；5）深入研究了单电源大容量异步SRAM中低压差线性稳压器（LDO）的辐射效应机理，通过重离子试验研究了LDO输出端的SET特性，并提出了加固技术完成了抗辐射加固LDO芯片的研制，设计实现了单电源大容量异步抗辐射加固SRAM。.本项目系统地研究了65nm CMOS工艺SRAM的低功耗和抗辐射加固设计技术，形成了高水平研究论文11篇，其中9篇为SCI检索论文（含4篇IEEE Transactions顶级学术水平论文）；申请了软件著作权4项。相关研究成果物化为国内首家在65nm CMOS工艺下成功研制的抗辐射单双端口SRAM和RF编译器，为在65nm CMOS工艺下成功构建抗辐射加固设计技术平台提供了重要基础。基于构建的65nm体硅CMOS工艺抗辐射设计加固技术平台，国内同行即可快速研制出满足中、高轨空间应用要求的抗辐射芯片，极大的提高了抗辐射集成电路的研制效率。研究成果促进了国内宇航用器件研制水平的跃升，对于打破国际技术壁垒，保障我国宇航用核心器件自主可控具有极其重要的战略意义。