基于贝叶斯优化的纳米尺度模拟集成电路设计优化方法研究

Design automation of analog and mixed signal systems such as phase-locked loop, data converter, or RF front-end is now facing the challenges including large circuit size with 10000 or more devices, quantum effects of nanometer devices and the statistical distributions of circuit performances induced by severe process variations under 10 nanometer CMOS process technology. Traditional analog design automation methodologies consume huge amount of CPU time and can hardly achieve qualified design satisfying with design specifications, which poses the bottleneck problem in analog design automation area. In this project, we proposed a Bayesian optimization theory for analog circuit synthesis which is a powerful methodology to significantly reduce the number of samplings for estimating the objective functions which is extreme time consuming. Therefore the Bayesian Optimization framework open a completely new direction for analog circuit synthesis. In this project, (1) we propose the Gaussian Process model based Bayesian optimization method which outperforms the existing global optimization methods like DE, SA, GA, PSO, MSP and GASPAD. (2) We propose the weighted Expected Improvement (wEI) criterion that multiplies EI by the possibility of satisfying the constraints to design the acquisition function by trading off the exploitation of the current promising area and the exploration of the search space. (3) We propose the gradient based optimization method like SQP (Sequential Quadratic Programming) to solve the minimization of acquisition function with multi-start local search since the gradient can be calculated analytically from the acquisition function. (4) We proposed an adaptive approach to partition the high dimension design space into regions and build GP mode in each region as well as employ Bayesian optimization parallelly among all regions. The proposed Bayesian optimization framework for analog circuit design automation will significantly reduce the simulation time and achieve high efficiency and high quality design, which will establish new theory and framework for the next generation analog design antomation tool for the semiconductor industry.

系统级模拟集成电路设计面临电路规模庞大、纳米器件模型复杂、电路性能统计分布的严重挑战。传统的模拟电路自动化优化方法耗时巨大，难以获得满足指标的电路设计，已成为集成电路设计的国际瓶颈问题。本项目提出基于贝叶斯优化的模拟电路综合方法，极大地降低了目标函数计算次数，为解决高维空间模拟电路非线性优化的科学难题建立了新方向。本项目（1）建立了基于高斯过程伴随模型的模拟电路贝叶斯优化方法，相比传统的方法如模拟退火、进化算法、粒子群算法、多起始点算法、GASPAD等，可以用更少点获得更优的优化结果；（2）提出将约束加权的改进期望函数作为贝叶斯优化中的获取函数，提高优化的可靠性；(3)提出了基于梯度的优化方法求解获取函数最优化问题；（4）提出设计区域的自适应划分及并行贝叶斯优化方法。本项目提出的贝叶斯优化理论和方法，大幅提升模拟电路优化的效率和性能，为模拟集成电路设计自动化建立了全新的理论框架和高效算法。

模拟集成电路设计面临电路规模庞大、仿真时间长、高维空间非线性规划、纳米工艺偏差的挑战。大规模模拟电路自动优化设计是长期企待解决的国际难题。本项目将贝叶斯推断和贝叶斯优化等机器学习的方法应用于集成电路建模、分析和优化，建立了基于贝叶斯优化的模拟电路优化设计方法、集成电路分析与成品率分析的统计方法、基于机器学习的可制造性和可靠性设计方法等，为大规模系统级模拟电路的分析与优化设计提供了全新的理论框架。..（1）提出了基于贝叶斯优化方法的模拟电路智能化设计方法，包括基于贝叶斯优化的模拟电路优化方法、多目标贝叶斯优化、多置信度贝叶斯优化、并行化贝叶斯优化、高效异步并行贝叶斯优化，基于贝叶斯优化与自适应成品率分析的模拟电路与SRAM成品率优化方法，论文发表在机器学习顶级会议ICML 和 DAC ，开发了模拟集成电路优化设计自动化工具，在上海安路、万众一芯等公司得到应用，为研发我国自主知识产权EDA工具提供了核心技术支撑。..（2）提出了基于贝叶斯推断和统计分析的集成电路失效率分析方法，包括基于伯努利分布贝叶斯推断的多工艺角成品率分析、不同工艺角大规模集成电路系统失效率分析、基于图的改进高效时序分析和优化方法。解决了多失效区域、多工艺角、系统级芯片极低失效率分析的瓶颈问题。研制了集成电路成品率分析工具，已在万众一芯公生物芯片设计成品率分析中应用。..（3）提出了基于机器学习的可制造性设计和可靠性设计方法，包括基于二值神经网络的光刻热点检测方法、通过将全芯片CMP仿真器迁移至卷积神经网络的基于模型哑元填充综合方法。研制了基于模型的化学机械抛光哑元金属填充工具，在华大九天获得应用。..发表论文26篇，SCI收录12篇、EI收录26篇。撰写1本专著的3个章节。国际权威期刊IEEE Trans. on CAD、IEEE Trans. on CAS I、IEEE Trans. on CPMT、IEEE Trans. on VLSI论文10篇、机器学习顶级会议ICML 1篇、EDA领域顶级会议DAC论文6篇。申请国家发明专利5项。4次国际会议邀请报告。