基于贝叶斯推断的纳米尺度集成电路统计分析方法研究

The severe process variations of the complex nanometer process technology cause the random variations of integrated circuit performance and the significant degradation of the chip yield. To validate the VLSI circuit performance considering process variation, a large number of data need to be collected by the traditional analysis approaches which result in computation explosion and can not be applied to stochastic analysis of real integrated circuits. How to analyze statistical performance using small data instead of big data has become a new research direction in the leading edge research for enhancing the chip yield. ..In this project, we propose a novel statistical framework, referred to as Bayesian Model Fusion (BMF), that allows us to minimize the simulation and/or measurement cost for both pre-silicon verification and post-silicon validation. The proposed BMF technique is motivated by the fact that today’s integrated circuits design cycle typically spans multiple stages. Our key idea is to reuse the simulation and/or measurement data collected at an early stage to facilitate efficient validation of integrated circuits with a minimal amount of data required at the late stage. Towards this goal, new Bayesian Model Fusion framework will be established to deal with discrete performance metric and multiple correlated performance metrics of integrated circuits, while only continuous performance metric and single performance metric have been established in the existing Bayesian Model Fusion methodology. The proposed new Bayesian Model Fusion framework will be employed to efficiently analyze four important industrial applications, including (1) efficient Bit Error Rate estimation for High-Speed Link, (2) efficient multivariate moment and yield estimation for Analog and Mixed-Signal Circuits, (3)Aging analysis of integrated circuits, (4) modeling of Chemical Mechanical Polishing of copper interconnect technology. Our preliminary results show that BMF is able to reduce the validation cost by 3~10x compared to other traditional methods. ..The proposed BMF technique provides a fundamental infrastructure that enables next-generation integrated design for nanoscale IC technology. It is expected to yield significant performance improvement for advanced electrical circuits in a broad range of applications, from consumer electronics to medical instruments. Hence, successful development of the proposed BMF framework will have both short-term and long-term impacts on the semiconductor industry.

复杂纳米工艺导致电路性能严重偏差，对集成电路成品率产生显著影响。为了验证集成电路统计特性，传统方法采集“大数据”来分析，其代价越来越难以承受。近年来如何采用“小数据”而非“大数据”来获得高精度的统计分析成为集成电路分析国际前沿研究的新方向。本项目提出贝叶斯推断的思想，利用集成电路在设计与制造不同阶段的电路性能的相关性，将设计早期的数据作为先验知识，与后期的小数据进行融合，高精度地推断电路性能统计分布特性、制造工艺特性等，极大地降低集成电路分析验证的成本。现有贝叶斯推断电路分析方法仅能分析电路的单个连续型性能参数，在实际应用中具有局限性。本项目将发展针对离散型性能参数的贝叶斯推断及多个性能参数的贝叶斯推断新理论和新方法，并应用于高速互连误码率分析、集成电路参数成品率分析、老化分析以及化学机械抛光工艺建模等，为下一代纳米尺度集成电路设计与制造的分析、验证、测试建立基础性的理论框架和高效算法。

针对集成电路进入纳米尺度所面临的时序收敛、计算量爆炸、成品率等国际难题，将贝叶斯推断、贝叶斯优化等机器学习的方法应用于集成电路建模、分析和优化，建立了基于贝叶斯推断的集成电路建模及分析方法、集成电路成品率的统计分析方法、基于贝叶斯优化模拟电路优化方法等，为解决集成电路设计复杂度问题、非线性优化问题提供了创新理论方法。.（1）提出了基于贝叶斯推断的集成电路的建模方法，包括多先验贝叶斯推断电路建模、基于核密度和稀疏先验的非高斯回归方法、基于贝叶斯推断和分层收缩分布的混合性能建模、基于贝叶斯神经网络的帕累托前沿建模、基于隐马尔科夫树的工艺偏差空间建模、基于稳健字典训练的工艺偏差空间建模。基于机器学习的工艺偏差空间建模技术在华为海思硅片测试中得到应用。.（2）提出了基于贝叶斯推断的多工艺角成品率分析方法、基于相关贝叶斯推断的多工艺角大规模集成电路系统失效率分析方法、基于渐进概率估计的系统级极低失效率分析方法、高维和多失效区域的SRAM成品率分析方法，解决了多失效区域、多工艺角、系统级芯片的成品率分析的瓶颈问题。研制了基于贝叶斯推断的集成电路成品率分析工具，已在万众一芯公司生物芯片设计得到应用。.（3）提出了基于聚类的电源地网络模型降阶方法，获得《Integration, the VLSI Journal》2018国际期刊最佳论文。研发了互连线模型降阶工具应用于我国最大的EDA公司华大九天。模型降阶工具已在华为海思7纳米设计中应用。.（4）提出了基于贝叶斯优化的模拟电路智能设计方法，获得DAC 2017最佳论文提名。开发了模拟电路设计自动化工具，在上海安路、万众一芯等公司得到应用，为研发我国自主知识产权EDA工具提供了核心技术支撑。.发表论文33篇，其中SCI收录16篇、EI收录30篇。撰写2本专著中的4个章节。国际权威期刊IEEE Trans. on CAD、IEEE Trans. on CPMT、IEEE Trans. on VLSI论文13篇、EDA领域顶级会议DAC论文7篇、机器学习顶级会议ICML 1篇。授权国家发明专利4项。获得2018年《Integration, the VLSI Journal》国际期刊首届最佳论文奖，获得UEMCOM 2017国际会议最佳论文奖，获DAC 2017、ASPDAC 2017国际会议最佳论文提名。6次国际会议邀请报告。