微结构建模驱动的千核级片上网络演算模型及其紧致性分析技术研究

With the development of manycore architectures, Network-on-Chip (NoC) emerges as the most promising candidate for the thousand-core on-chip interconnect design. For applications that have quality of service (QoS) requirements on NoC based manycore system, network calculus based performance bound analysis has been proved to be effective. When scaled to thousand-core size, either the performance analysis or tightness evaluation will experience dramatically increased complexity. Thus, it has stringent requirements of developing the thousand-core NoC oriented modeling, analysis and tightness evaluation methodology, which will support the development of domestic high performance manycore chips..This proposal aims to build the unified micro-architectural modeling framework of network design and calculation model for the thousand-core NoC. We put forward the end-to-end delay analysis model for the retransmission scheme in case of lossy links. Joint tightness of delay bound and backlog bound is studied. The whole flow of network calculus based modeling and analysis is to be automated and integrated into the model developing tool. Furthermore, machine learning based method will be incorporated into the tightness study procedure to promote the analysis efficiency in the thousand-core era. The research will provide an effective modeling and performance analysis method for the onchip interconnect of the thousand-core chips, and hammer a solid basis of theory and techniques for the domestic high performance manycore chips in the near future.

随着众核体系结构的发展，片上网络（NoC）已经成为千核级芯片互连设计的必然选择。针对实际应用对NoC服务质量（QoS）的要求，采用网络演算模型对NoC通信的性能界进行分析被证明是很有效的方法。但是千核级NoC从性能分析到模型紧致性评估的复杂度都显著增加了，研究面向千核级NoC的建模、分析与模型紧致性评估方法对国产众核芯片的研制具有重要意义。.本项目面向千核级NoC构建网络设计与演算建模一体化的微结构建模框架，针对有损失链路的数据重传机制提出端到端延迟分析模型，对演算建模与分析的全流程进行自动化及工具集成，并在此基础上研究延迟界与缓存积压界模型的联合紧致性，开发基于机器学习的对演算模型紧致性分析过程进行优化的方法，实现从微结构模型出发对千核级NoC进行设计、演算分析及紧致性评估的自动化流程。为千核级处理器的片上互连提供高效的建模手段与性能分析方法，为研制高性能众核处理器奠定坚实的理论基础。

针对众核体系结构中对NoC服务质量（QoS）的要求，采用网络演算模型对NoC通信的性能界进行分析被证明是很有效的方法。研究面向千核级NoC的建模与分析方法对高性能众核芯片的研制具有重要的意义。.本项目面向千核级NoC构建网络设计与演算建模一体化的微结构建模框架，对演算建模与分析的全流程进行自动化及工具集成。对xMAS建模组件进行了扩展，并在RTL级对经典的网络调度算法，例如Weighted Round Robin (WRR)、Weighted Fair Queuing (WFQ)、Self Clocked Fair Queuing（SCFQ）等，进行了实现和验证。此外，开展了机器学习模型的建模与训练研究并应用到了SoC芯片的物理设计中。本研究将为千核级处理器的片上互连提供了高效的建模手段与性能分析方法，为将来国内自主研制超高性能众核处理器奠定坚实的理论与技术基础。