三维晶片堆栈封装的底部填充关键技术的研究

3D chip stacking with through-silicon-vias (TSVs) has emerged as a solution for smaller package footprint and higher device performance. The 3D chip stack package is generally flip mounted onto an organic substrate. In order to enhance the reliability and the sealing performance of the chip stack package, underfill encapsulant should be applied into the gap among two adjacent chips or between the bottom chip and the substrate. However, current methods have no effective solutions to accomplish the underfilling of all gaps of the 3D chip stack package. During the course of study, a novel underfill dispensing method using TSVs (TSV underfill dispensing) will be comprehensively investigated in order to address the underfill challenges on 3D chip stacking. TSV underfill dispensing is applied after package assembly. The TSVs function as entrances for fluid dispensing or paths for fluid flow. This study will first investigate the rheological properties and the capillary characterizations of some typical encapsulants, and construct proper mathematical models for them. Then, an analytical model will be investigated for constructing the parameter correlation among the material properties, filling time, the inflow boundary and the package geometries. The study of parameter correlation can help optimize TSV underfill process to obtain shorter filling time. Besides, the stacked chips in a 3D chip stack package are usually the same size and are vertically aligned during the chip bonding process. The planar sidewalls of the 3D chip stack package can function as “outlets” if the underfill flow around the chip edges breaks through the sidewalls and flow downwards, or function as “walls” if the underfill flow is constrained in the gaps. The transition from the “walls” to the “outlets” and the reason of an edge flood failure will be deep investigated. After confirming the boundary conditions of the sidewalls, numerical simulations (using CFD tools) will be constructed to simulating the fluid flow during the TSV underfill process. The simulation results can provide design criteria for TSV distributions and dispensing steps. Finally, a 3D package with die/interposer stacking and TSVs will be developed for concept validation. The effect of TSV underfill dispensing on the 3D die/interposer stack package will be observed by SAM evaluations and cross-section inspections.

三维晶片堆栈封装属于下一代电子封装技术，符合电子产品日益微型化和多功能的发展趋势。为了提高封装器件的可靠性和密封性，晶片之间的间隙、晶片与基板之间的间隙，都需要用进行底部填充。然而，目前尚无有效方法对其进行完整的底部填充。本项目旨在研究一种新的、基于硅通孔的底部填充方法。填充材料将通过顶层晶片的硅通孔注入，而晶片堆栈内部的硅通孔则作为不同层之间的流动管道。本项目将首先对常用填充材料的流变性质和毛细特征进行评估和建模，然后为单层流动建立理论模型和参数联系，以探讨影响本方法填充时间的关键因素。当通过硅通孔填充三维晶片堆栈时，主要的问题是填充材料可能从晶片边沿溢出。本项目将深入探究边沿溢出的原因，并确定其产生的临界条件。之后，结合此临界条件和两相流模型，利用流体仿真工具，确定硅通孔分布的设计准则和相对应的填充步骤。最后，本项目将研制三维晶片堆栈封装的样品，并进行实验验证以及各种评估和测试。

三维晶片堆栈封装作为下一代半导体封装技术，满足了电子产品日益多功能和微型化的要求。为了提高三维晶片堆栈封装的可靠性，晶片之间的间隙、晶片与基板之间的间隙，需要用填充材料进行完整的底部填充。目前三维封装已广泛采用硅通孔来实现电气垂直互联。在此背景下，本项目研究了一种新的、基于硅通孔的底部填充方法，来解决三维晶片堆栈所面临的底部填充难题。基于硅通孔的底部填充，填充材料是通过顶层晶片的硅通孔注入或滴入，它可以完全兼容当前表面贴装工艺和自动化产线，因此无需投入新的成本来升级当前的设备。本研究的首先通过对填充材料的流变性质和毛细特征的表征，确定了Guggenheim-Katayama表面张力模型、多项式静态接触角拟合、Power-Law粘度模型和Newman接触角的动态变化模型。填充材料的毛细流动一般比较缓慢，因此填充时间是底部填充制程的关键。在材料表征和建模的基础上，本项目继而为填充材料的一般单层流动构建了解析模型。研究表明，一般毛细流动的填充时间和焊点分布系数、剪切粘度、填充半径成正比，而与晶片间隙、表面张力系数、动态接触角、硅通孔直径成反比。当填充多层晶片堆栈时，最主要的问题是填充材料可能从晶片边沿溢出。实验表明，为了避免边沿溢流失效，边沿流的压强应低于极限平衡压强。极限平衡压强通过杨-拉普拉斯方程和流动前界面曲线的曲率方程确定。在获取材料模型、一般毛细流动模型和边沿溢出的临界条件后，本项目进而通过多相流仿真，最终得到了一种优化的硅通孔分布，用于实现多层晶片堆栈的底部填充。最后，包含四层堆栈结构的样品被制备，固化后的三维晶片堆栈样品，通过各种分析，证实了样品的完整性和基于硅通孔底部填充方法的可行性。