FPGA嵌入式抗辐照容错处理器核及其系统设计实现研究

A modern high-performance FPGA or a network on chip (NoC) based on it generally contains embedded processors in addition to programmable logic and interconnect resources. In high radiation environments like aerospace, satellites, nuclear devices, military communications, a sub-micron FPGA is subjected to high-energy particle strikes, resulting in transient or permanent errors in its programmable logic and interconnect resources and embedded processors. The radiation tolerant design for the programmable logic and interconnect resources has been widely researched and is not the target of the project. This project targets the FPGA embedded fault tolerant processors. This project will conduct research into fault tolerant coding algorithms and high-speed radiation tolerant hardware for a single processor, fault masking and repair for double or triple processors, and fault-tolerant reallocation, rerouting and flow control for a many-processor network. An FPGA can combine these techniques and adaptively selects fault-tolerant schemes according to the number of faulty processors. The proposed schemes will be validated via fabrication and modelling.

现代高性能FPGA或基于它的片上网络（NoC）除含有可编程逻辑互连资源外，往往包含单个嵌入式处理器核或多个处理器核构成的系统或网络。在太空探索，空间卫星，核电辐射，军事通信等高辐射环境中，深亚微米级的FPGA很容易受到大量高能辐射粒子撞击，引起其中可编程逻辑互连资源和嵌入式处理器核出现暂时或长期错误。可编程逻辑互连资源的抗辐照设计已经获得大量研究，不是本课题研究重点。本课题主要研究FPGA中嵌入式抗辐照容错处理器核及其系统设计。本课题基于已有的FPGA和处理器的软硬件设计经验，研究FPGA中单处理器核的容错软件代码生成算法和高速抗辐照硬件结构，双或三处理器核系统的错误屏蔽和修复技术，多处理器核网络的容错重分配，重路由和流控技术。FPGA可把这些适合不同处理器数量的容错技术结合起来，根据错误处理器核数量，自适应调整容错策略，快速克服错误处理器核的影响。本项目将做实例芯片的流片验证和建模。

现代高性能FPGA除含有可编程逻辑互连资源外，往往包含单个嵌入式处理器核或多个处理器核构成的系统或网络。在太空探索，空间卫星，核电辐射，军事通信等高辐射环境中，深亚微米级的FPGA很容易受到大量高能辐射粒子撞击，引起其中可编程逻辑互连资源和嵌入式处理器核出现暂时或长期错误。本项目研究FPGA中嵌入式处理器核及可编程资源的抗辐射硬件电路结构和软件算法。我们提出了适用FPGA嵌入式处理器核及可编程资源的抗辐射触发器电路、抗辐射分频电路、多处理器核温度敏感的线程分配算法、抗辐射布局布线算法和渐进冗余优化算法。这些方案可以在提高FPGA嵌入式处理器核及可编程资源抗辐射能力的同时，还能保持其高速或高频性能。