芯片指纹PUF电路关键技术研究与验证

With advances in chip attack technology, chip fingerprint, which is stored in non-volatile read only memory (ROM) and other media, can easily be intercepted through physical attacks such as layout reconstruction and microprobing technique, and is copied. As a result, the emergence of a large number of clone chips destroys healthy development of China's IC industry. Physical unclonable function (PUF) has good characteristics of security and unclonable, which means PUF can effectively resist physical attacks and is difficult to be reproduced, therefore, it is being gradually applied to the field of chip fingerprint generation. However, traditional PUFs for chip fingerprint generation have relatively bad uniqueness and reliability, due to the limitations of PUF cell, the architecture, reliability enhancement mechanism, and other aspects..With the goal of improving the uniqueness, for one thing, a new PUF cell is proposed, based on a new method of enhancing the sensitivity of PUF cell to process variation. For another, a new diffusion algorithm is designed to transform ID bits, which ensures that transformed IDs satisfy the requirement of uniform statistical distribution in a large numerical space. With the goal of improving the reliability, firstly, a new PUF architecture is proposed. It is composed of three circuit components, including process sensors, difference amplifier and difference comparator. Secondly, a new voting mechanism is implemented in the project, which is used to sample the output of the comparator many times, and produce a stable ID bit based on 0/1 probability distribution. With the goal of improving the security, layout design techonologies including symmetrical layout, equal-length wiring and special top s-type mesh routing are studied. Aim at resisting physical attack of layout reconstruction, symmetrical layout and equal-length wiring is discussed. Aim at resisting physical attack of microprobing technique, special top s-type mesh routing scheme is proposed. Finally, based on research of these key technologies, Current Starved Delay Element-based PUF prototype chip is designed and fabricated in 0.18μm CMOS technology.

随着芯片攻击技术的发展，存储于ROM等非易失介质中的芯片指纹很容易通过版图反向工程和微探测技术等物理攻击方式被截取并且被复制，导致大量的克隆芯片出现而破坏我国集成电路产业的良性发展。物理不可克隆函数（PUF）电路具有良好的安全性和不可克隆性，能够有效地抵御物理攻击且很难被复制，因此它正在逐步地被应用于芯片指纹生成领域。而已有的芯片指纹PUF电路在PUF单元、体系结构和可靠性增强机制等方面的设计存在局限性，导致PUF的唯一性、稳定性等性能都较差。.本项目通过研究新型的PUF单元和指纹ID扩散算法，增强芯片指纹PUF电路的唯一性；通过研究新型的PUF体系结构和表决机制，增强芯片指纹PUF电路的可靠性；通过研究对称布局和等长走线、以及特殊的顶层S型网格布线等版图实现技术，增强芯片指纹PUF电路的安全性。最后基于这些关键技术，在0.18μm CMOS工艺下设计和验证芯片指纹PUF电路原型芯片。

随着芯片攻击技术的发展，存储于ROM等非易失介质中的芯片指纹很容易通过版图反向工程和微探测技术等物理攻击方式被截取并且被复制，导致大量的克隆芯片的出现而破坏我国集成电路产业的良性发展。物理不可克隆函数（PUF）电路具有良好的安全性和不可克隆性，能够有效的抵御物理攻击且很难被复制，因此它正在逐步的被应用于芯片指纹的生成领域。本项目围绕芯片指纹PUF电路关键实现技术展开研究，主要研究内容包括芯片指纹PUF电路唯一性增强技术、芯片指纹PUF电路稳定性增强技术与芯片指纹PUF电路安全性增强技术三个方面，研究结果包括设计实现了基于电流饥饿型延迟单元的新型PUF单元，新型的PUF体系结构，新型的指纹ID扩散算法，优化的表决机制算法，对称布局和等长走线、以及特殊的顶层S型网格布线版图实现技术；同时通过研究器件尺寸和宽长比与器件mismatch 特性之间的关系，修正了器件物理特征参数的Mismatching 模型，通过选择器件最优尺寸增强PUF单元的工艺敏感性；提出了基于量化延迟特性对温度和电源电压求导在拐点处获取相关设计参数最优值的PUF 单元稳定性增强方法；最后在0.18μm CMOS工艺下设计实现了一款基于电流饥饿型延迟单元的芯片指纹PUF电路原型芯片。本项目在器件Mismatching 模型与ID扩散算法方面的研究具有很强的科学意义，修正后器件Mismatching 模型不仅同器件尺寸WL而且同器件宽长比W/L有关，改善了器件mismatch特性计算的精确度；ID扩散算法基于ID统计规律结合异或去相关原理设计，对指纹ID 进行散列化和随机化，使得扩散后的ID 在一个大数值统计空间内满足均匀分布，增大了ID 之间的海明距离，去除相关性。