基于碳纳米管空间扰动特性的碳基集成电路高良率设计技术研究

Carbon nanotube (CN) transistors are promising candidates for future very large scale integration (VLSI) circuits due to their small footprint and high performance. However, the severe process variations of carbon nanotubes have significantly degraded the circuit yield. Furthermore, the circuit design complexity is also exacerbated by the spatial correlation and specific electrical characteristics of carbon nanotubes. Unfortunately, the existing carbon-based circuit design are still primarily based on the conventional silicon-based circuit design techniques, which have great limitations on the improvement of yield. To solve this problem, we propose the hierarchical co-design method across three different levels “device-circuit-layout placement”. We develop the high-yield circuit design techniques by following the “yield modeling-functional yield enhancement-parametric yield enhancement” mainline. Based on the specific process variations, we establish the circuit functional yield models by considering multiple variation parameters. By leveraging the spatial correlation and partitional clustering method, we propose the multiple-dimensional redundancy device structures and optimization algorithm of circuit placement for achieving high functional yield with low area and power overheads. By taking the advantages of symmetrical electrical characteristics of n-type and p-type carbon nanotube transistors, we design the robust circuit topologies and variation-tracked auxiliary circuits that are well applicable to carbon nanotube transistor technology. Furthermore, with the aid of circuit and layout co-design, the parametric yield can be enhanced. The results can provide new ideas and solutions for realizing the high-yield carbon-based VLSI circuits, which can meet the requirements of mainstream applications and promote the progress of industrialization. The results can also be used as a reference of circuit design with other emerging transistor technologies.

碳纳米晶体管以其尺寸小及性能高的优势，成为实现未来超大规模集成电路的理想器件。但碳纳米管具有与传统硅不同的特殊工艺扰动，导致电路良率低；其独特的空间相关性和电学特性，加剧设计复杂度。然而现有碳基电路研究仍延用传统硅基电路技术，对提升良率具有很大局限性。对此，本项目基于碳纳米管空间扰动特性，提出“器件-电路-版图布局”的跨层次协同设计思路，以“功能良率建模-功能良率提升-参数良率提升”为主线，研究高良率电路设计技术：建立多元扰动参量的电路功能良率模型；利用空间相关性和聚类划分思想，提出具有高功能良率、低面积和功耗开销的器件多维冗余结构及电路布局优化算法；设计适用于碳基工艺的电路拓扑结构和外围扰动跟踪电路，并借助于电路与版图协同设计，有效提升电路参数良率。项目成果可望为实现满足应用需求的高良率碳基集成电路提供新思路和方案，对其迈向产业化起到积极推动作用，也为其它新工艺电路设计研究提供参考。

随着超大规模集成电路的特征尺寸缩小至亚10纳米工艺节点，传统硅基CMOS集成电路面临性能和物理极限。碳纳米晶体管（CNFET）具有尺寸缩小能力强和能效高等显著优势，成为未来集成电路晶体管的最有潜力的替代技术之一。然而现阶段碳纳米管工艺技术尚未成熟，无法精确控制碳纳米管的生长属性，以金属型碳纳米管和碳纳米管直径扰动为首的工艺扰动，严重影响了碳基电路良率和性能。为了克服当前碳基电子工艺扰动给大规模集成电路量产所带来的瓶颈问题，本项目通过系统分析碳纳米管工艺扰动空间特性，建立了具有普适性的碳基电路功能良率模型；以片上缓存即静态随机存储器（SRAM）为主要电路研究对象，结合碳纳米管空间扰动特性及电学特征，全面分析了当前硅基电子中常用的标准6管SRAM以及8管SRAM电路等存在的挑战，综合考虑电路的功能良率、读写性能/裕量、功耗和面积，展开了从碳基器件尺寸、存储器结构到版图的协同设计和优化，并且利用CN工艺扰动的空间相关性，对关键CNFET进行版图关联耦合，有效减小了工艺扰动对存储器读写性能的影响，显著降低了存储器的读写失效率，极大提升了碳基电路功能良率，其中所实现的电路设计方法将业界标准6管SRAM电路的功能良率从原来不到1%提升到97%以上。为了进一步提升碳基电路集成度，本项目基于CNFET低温制造工艺天然适合于单体三维 (Monolithic Three-Dimension, M3D) 集成技术这一特质，将二维碳基集成电路设计技术延伸和拓展至了单体三维碳基集成电路设计技术，提出两种新型的碳基8管SRAM单元结构，将存储阵列集成密度提升高达89.92%。本项目所研究的碳基电路设计技术有效解决了工艺扰动给碳基集成电路带来的良率瓶颈问题，对碳基电路产业化起到积极的推动作用，也为其它新型半导体工艺技术的集成电路设计提供参考。