基于GPU的提高三维集成电路良率的测试数据优化方法研究

The shrinking silicon feature size and the continuously growing transistor count not only increase computation capability (especially parallel computing capability) of the (multi-core or many-core) chip, but also caused complicated faulty behaviors of a circuit which results in the huge challenges to VLSI testing. Existing test applications (such as test generation and test compression) running for the large industrial designs consume such a long CPU runtime that the test applications have to be truncated, incurring less than optimal test coverage and huge test volume. In comparison to 2D IC, the complicated defects induced by the new process technique in 3D IC have much more complex behaviors and result more kinds of fault models. So, the efficient algorithm of optimizing or selecting high quality tests is then critical for test application in 3D IC. Beside the existing researches of the yield of 3D IC focus on test flow optimization or analysis/modeling on die level, this project targets on GPU-based efficient test set optimization techniques to increase/remain the overall 3D-IC yield. The project is consist of the following three parts: 1) a GPU-based fault simulation for different kinds of fault models to generate the fault table which can be used to evaluate the test quality of a test set and a key step of the test set optimization; 2) for the test set excluding don’t-care (‘X’) bits, an efficient test selection technique with tuning the defect level of the sub-circuits locating on different layers to keep high yield of overall chip. During the test selection, the tests are ordered by their contribution to the defect level so that they can detect more defected chips in the early time of test application and reduce the test cost; 3) an efficient GPU-based test set optimization technique, with exploiting don’t-care bits of the test pattern to detect more faults, to generate a small & high test-quality test set and achieve high yield of 3D IC.

工艺尺寸细化和片内晶体管数量速增在不断增强芯片并行性能同时，也造成集成电路（IC）缺陷越发复杂，给IC测试带来巨大挑战。现有测试程序在运行工业电路时因耗时过多而被裁剪，导致海量测试数据（测试向量集）和非最优故障覆盖率。3D IC缺陷比传统IC更复杂繁多，测试程序时间过长及测试向量集过大的问题更为严峻。本课题围绕3D IC良率和测试成本，利用GPU并行性能，高效获得给定测试成本下的高质量的测试数据，分为三部分：1）基于GPU面向多种故障类型的故障模拟，其产生的故障检测表可评估测试质量，是测试优化基础；2）面向不含无关位的测试向量集，利用GPU从中选择容量小且较高测试质量的测试向量集，调节不同层晶片的良率，最终优化3D IC整体良率；3）基于GPU的提高3D IC良率的测试集优化，在选择高质量的测试向量同时，结合无关位填充优化该测试向量检测故障能力，最终优化测试成本和良率。

三维集成电路以较低成本实现逻辑模块的堆叠，提高电路集成度，还能缓解二维电路互连线延迟和功耗的瓶颈。通过将多组内存模块与计算逻辑电路集成到一个芯片中，内存计算(PIM)可以使得数据运算可以就近在存储器上进行，应对“存储墙”问题，减少处理器和存储器之间的密集数据传输而造成的性能和功率损失，PIM已经被认为是最可能解决存储墙的方案，尤其在是访存密集型的图计算和数据分析。然而，当未来计算系统变得越来越可能采用PIM体系结构作为一种存储和处理组件时，目前只有针对专用PIM设计的任务划分方式，仍然缺少面向通用PIM架构的任务调度方法。本项目提出了一种形式化的通用模型来量化多核CPU+PIM的异构系统的多任务调度问题，同时提出了一种任务调度优化算法，以提高这些新型异构系统的硬件利用率。所提出的调度算法充分考虑了CPU和PIM设备之间的数据访问带宽和各自的计算处理能力，以及任务映射对并发工作负载的访存带宽竞争、数据通信强度和硬件利用率的影响。实验结果表明，与传统的异构系统调度算法相比，所提出的方法能够提高了超过10%的系统性能，提高了大约10%的能效性。