面向3D芯片良率提升的TSV复用容错关键技术研究

Through-Silicon Via (TSV) is easy to introduce various kinds of defects in the process of manufacturing、thinning and bonding, which makes the yield of 3D chips far lower than expected. Adding redundant TSV is an effective method to improve the yield of 3D chip, but the area of redundant TSV is high and the manufacturing cost is expensive. The 3D chip includes not only the function TSV for signal transmission, but also the testing TSV for testing data transmission. In normal function mode, testing TSVs can be regarded as redundant TSVs. Regarding this, the project plans to study TSV fault-tolerant methods based on TSV multiplexing, which can improve the yield of 3D chips at low cost. This project intends to study the time division multiplexing access (TDMA) based function TSV multiplexing and the testing TSV multiplexing fault-tolerant method at the circuit level; and the placement optimization of TSV multiplexing at the algorithm level. This project explores the fault-tolerant mechanism of TSV multiplexing, without adding redundant TSV, the existing TSV (function TSV, testing TSV) can be configured and reused online according to fault information to realize TSV fault-tolerance. The cost of fault-tolerant can be reduced and the flexibility of fault-tolerant design can be enhanced on the premise of improving 3D yield. This project is of great significance to reveal the fault-tolerant mechanism of 3D chips. It has important theoretical and practical significance to improve the yield of 3D chips, improve the fault-tolerant methodology of integrated circuits and promote the industrial application of TSV fault-tolerant schemes.

硅通孔（TSV）在制造、减薄、绑定等过程中会易引入各类缺陷，使得3D芯片良率远低于预期。添加冗余TSV是提升3D芯片良率的有效方法之一，但冗余TSV面积开销大、制造成本高。3D芯片中不仅包括用于信号传输的功能TSV，还存在用于测试数据传输的测试TSV，在正常功能模式下，测试TSV可被视为冗余TSV。对此，本项目拟计划研究基于TSV复用的容错方法，低成本实现3D芯片良率的提升。本项目拟在电路层研究基于时分复用的功能TSV复用容错方法以及基于测试TSV复用的容错方法；在算法层研究TSV复用的布局优化。本项目探索TSV复用容错机制，在不添加冗余TSV的情况下，根据故障信息在线配置复用现有TSV（功能TSV、测试TSV）实现故障TSV的在线容错，在提升3D良率的前提下可以降低容错成本、增强容错设计的灵活性。本项目为提升3D芯片的良率，完善集成电容错方法学，推进TSV容错方案的工业应用具有重要意义。

针对硅通孔（TSV）在制造、减薄、绑定等过程中易引入各类缺陷，使得3D芯片良率远低于预期等方面问题，本项目采用基于时分复用的功能TSV复用容错方法；基于测试TSV复用的容错方法；TSV复用容错布局优化等方法，对功能TSV、测试TSV进行合理布局优化，促进与推动新型3D芯片的研究与发展。提出了基于时分复用的功能TSV复用容错方法，对功能TSV进行复用可以避免添加冗余TSV，从而降低冗余TSV带来的硬件开销，解决了在工作模式下对功能TSV进行分时复用的关键问题。提出了基于测试TSV复用的容错方法，在正常功能模式下，测试TSV可以被视为冗余TSV。解决了对测试TSV进行复用的关键问题。提出了TSV复用容错布局优化的方法，对3D芯片TSV布局设计阶段进行功能TSV和测试TSV位置调整，从而优化扫描链的长度、所需复用TSV的数目和TSV修复路径的长度，对功能TSV和测试TSV进行了合理布局。共发表论文35篇，其中SCI收录22篇，EI收录10篇。在IEEE Trans. on CAD、IEEE Trans. on VLSI、IEEE Trans. on Emerging Topics in Computing、IEEE Trans. on CAS-I、IEEE Trans. on CAS-II等国际权威期刊上发表IEEE期刊论文14篇，授权国家发明专利11项。获 Asian Hardware Oriented Security and Trust Symposium 2022 (AsianHOST 2022) Best Paper Award，获CCF-腾讯犀牛鸟创意基金，获第十一届中国计算学会中国测试学术会议最佳论文（第1名）。