众核处理器片上网络的功耗优化方法研究

Networks-on-Chip (NoC), due to its abundant bandwidth and superior scalability, has become the major direction in developing on-chip interconnect of many-core processors. However, along with the rapid growth of transistor integration, power consumption of NoC is increasing dramatically as well. This proposal then focuses on the NoC power optimization strategies, and plans to resolve NoC power problems from three dimensions: (1) at node level, we propose to use link reconfiguration to tackle the connectivity issues introduced by the deployment of power gating techniques, and prolong the sleeping cycles of on-chip routers; (2) at sub-network level, the bandwidth and supplying voltage and frequency is proposed to be dynamically tuned, based on the analysis of application runtime phase changes, in an attempt to preserve application network performance and at the same time reduce power consumption; (3) at system level, we propose to optimize core and NoC power consumption in an coordinated way through observation of the correlation between core and NoC performance counters, and finally attain system-level power efficiency. Based on the three layer power optimization strategy, a series of creative solutions, such as shuttle NoC, traffic pattern prediction etc., are proposed to explore the bottom line of NoC power reduction and eventually boost the power efficiency of the entire many-core processor.

片上网络，由于能提供较大数据传输带宽和良好的可扩展性，是众核处理器片上互连的主要发展方向。然而，随着集成电路工艺的细化和处理器规模的不断增大，片上网络的功耗开销也在大幅增加。本项目主要面向片上网络的功耗优化方法，并计划从节点级、子网级和系统级三个角度提出跨层的功耗优化解决方案：（1）在节点级，通过链路重构，解决门控功耗技术带来的连通性破坏问题，降低门控功耗技术的性能开销；（2）在子网级，通过对应用程序运行阶段的预测分析，动态改变子网的带宽和供电电压、频率，在保证应用程序网络性能需求的同时降低功耗；（3）在系统级，通过分析处理器核与片上网络性能指标的相关性，对两者的功耗进行协同优化，达到系统级的能效最优。通过节点级，子网级和系统级的跨层功耗优化解决方案，提出了包括穿梭片上网络体系结构，数据流形态预测技术等多项创新方法，用于探索片上网络功耗降低的下限，并提升众核处理器系统的整体能效。

随着集成电路工艺进入亚微米时代，芯片的集成度越来越大，功耗逐渐成为制约众核处理器能效的首要因素。处理器的能效分为“计算”的高能效与“通信”的高能效，分别针对片上两大功能单元——处理器核（core）与片上网络（NoC）。近年来，针对处理器核的能效技术层出不穷，例如，采用动态电压与频率调整（DVFS）技术根据应用程序在不同阶段对处理器核的需求来调整核的能效。然而，针对片上互连的能效技术却没有实质性进展，原因在于片上互连负责核与核之间的通信以及应用程序在访存缺失之后访问主存储器，数据流的分布往往无法预测。本项目意在通过细粒度的功耗管理，在节点级控制片上网络的能效，进而提升整个众核处理器的能效。研究成果包括（1）基于穿梭片上网络的节点级功耗管理办法（已发表于CCF A类期刊TCAD上），（2）子网划分与节点级功耗管理技术（已发表于CCF A类期刊TCAD上），（3）众核处理器核级功耗管理技术（已发表在权威会议ASPDAC上）。项目成果包括：7篇会议、期刊论文，其中CCF A类2篇，B类3篇；相关成果可以在未来5年内全面应用到我国自主研发众核处理器的进程中。