低功耗InP/InGaAs垂直复合沟道MOSFET器件研究

Because of its high electron mobility ,InGaAs has become one of the candidates of the N-type channel material to extend Moore’s Law . An important issue for application of InGaAs MOSFET devices need to be overcome is that working at as low static power consumption as silicon devices. The target of this study is to manufacture the InGaAs MOSFET which has a same level of static power of the silicon CMOS. To solve the larger Ioff of the InGaAs MOSFET caused by the small band gap of InGaAs , in this study, using the InP/InGaAs vertical compound channel structure , the gate recess dry etching and data etch technology, fabricating the drain region by ion implantation, making out the large gate length device , summarizing the law of the device drain current at the off state and carrier mobility changing, taking out a perfect device integrated process, the gate length of 100 nm enhancement mode and low-power InP/InGaAs vertical compound channel MOSFET device will be fabricated.

InGaAs以其高电子迁移率，成为近年来被微电子业界寄予延展摩尔定律厚望的新型N型沟道材料。实现与硅器件相当的低静态功耗工作是InGaAs MOSFET器件实用化中需要克服的重要问题。本研究以制作出与硅基CMOS具有相同水平静态功耗的InGaAs MOSFET器件为目标，针对由于InGaAs禁带宽度窄导致的的器件关态电流大的难题，通过对InGaAs MOSFET器件结构和集成工艺两个方面进行创新，采用InP/InGaAs 垂直复合沟道器件结构，并利用TCAD软件进行参数优化，采用刻蚀、数字腐蚀相结合的工艺手段优化栅槽，采用离子注入工艺形成漏电极区以降低寄生电阻，并制作大尺寸InGaAs MOSFET器件，总结器件关态漏电流、载流子迁移率、阈值电压的变化规律，形成稳定的器件集成工艺，研制完成栅长100nm、增强型、低功耗InP/InGaAs 垂直复合沟道MOS原型器件。

本项目主要针对与硅器件相当的低静态功耗工作这一InGaAs MOSFET器件实用化中需要克服的重要问题。以制作出与硅基CMOS具有相同水平静态功耗的InGaAs MOSFET器件为研究目标，通过对InGaAs MOSFET器件结构和集成工艺两个方面进行创新，解决了InGaAs禁带宽度窄导致的的器件关态电流大的难题。本项目采用InP/InGaAs 复合沟道器件结构，并制作大尺寸InGaAs MOSFET器件，对IngAas沟道MOSFET器件的电学特性进行了深入研究，总结器件关态漏电流、载流子迁移率、阈值电压的变化规律，形成稳定的器件集成工艺，研制完成栅长100nm、增强型、低功耗InP/InGaAs 复合沟道MOS原型器件，实现了项目研究目标，完成了一套基于InP/InGaAs 复合沟道MOSFET器件的工艺技术，推进了InGaAs沟道MOSFET器件技术的基础研究。