片上网络功耗-性能空时特性分析及功率最优化动态分配方法研究

Powerful networks-on-chip-based multi/many-core chip systems have found wide applications in various areas that are thirst for performance. The ever increasing chip performance, however, comes with explosive growth in power consumption. It has been perceived that this power problem will soon escalate to a very dangerous point that the peak power request of a many-core chip will well exceed its power budget. Consequently, a large percentage of the transistors (up to 50%) in future chips may have to be powered off, which obviously have severely adverse implications on the chip performance. Such power-budget-induced performance problem becomes even much harder to address, given the fact that the chip power budget itself actually varies from time to time (i.e., with temporal variation) and from location to location (i.e., with spatial variation). In the literature, there has been little work that attempted to tackle the problems that are, for the first time, formally defined in this proposal. Starting from the spatial-temporal characteristics of power budget, this proposal herein proposes to develop a scheme that allows a many-core chip's power consumption to be adaptively adjusted so that it can conform to its power budget while achieving optimized overall chip performance. As so, novel solutions are proposed, including, 1) a highly parametric performance-power model perceiving power budget variations, and including various variables which can be tuned to optimize performance and power tradeoffs, 2) an adaptive power allocation approach which employs the top-down layered decomposition and distributed computing methods to reduce computation time and complexity. 3) Then by means of software simulation and hardware emulation, the accuracy of the model, the power allocation methods shall be evaluated and validated. The research of this proposal can promote the study on power adaptive on-chip architecture and energy-efficient computing.

基于片上网络的多核/众核芯片广泛应用于各领域。其性能不断增长的同时功耗亦快速增长。因功率预算无法满足未来半导体芯片峰值功耗需求，片上很大一部分晶体管将不得不停止工作。如何在功率预算受限情况下，使系统功耗适应功率预算，并优化性能，成为亟需解决的问题。而且，功率预算随时间和空间变化，使该问题异常复杂。 本课题以功率预算空时特性为切入点，旨在研究如何根据该特性进行优化功率分配，优化系统性能。 拟通过建立感知功率预算时间和空间变化特性的众核系统性能-功耗模型，考虑多种众核系统结构、参数、应用特性，可调节众多变量，提高性能和功率控制范围；在模型的基础上，动态功率分配方法采用自顶向下层次化分解和分布式计算的方法，降低功率分配计算实时求解的开销和复杂度。并进行软件仿真和硬件模拟验证，评估模型准确性、功率分配方法有效性和可行性。 可作为进一步研究功率自适应片上系统的线索，亦可推进高效能计算研究。

本课题主要研究片上网络性能-功耗模型，并根据该模型，定义如下研究问题：在给定的系统功率约束下，如何进行实时功率预算分配（分配给每个处理器、路由器等），从而使得整体系统性能最优。在本项目执行期间，课题组在经费的支持下，完成了大量研究工作。所取得的成果在IEEE Transactions on Computers（CCF推荐A类期刊）, IEEE Transactions on VLSI，ACM Transactions on Embedded Computing Systems（CCF推荐B类期刊），NoCS（片上网络领域著名会议），ASP-DAC（设计自动化领域著名会议）等高水平期刊、会议上发表了10余篇论文。本项目在以下几个领域取得了一些研究进展：.1..开发了并行仿真器PMS，可以模拟几百至上千核规模的众核系统。PMS仿真器采用多个子仿真器进程并行模拟，每个子仿真器进程通过网络仿真器进程进行数据通信和同步，保证了时序(timing model)和功能(functional model)的正确，可以在组网的多台服务器上运行上千核规模的仿真。同时，移植和开发了大量评测程序，包括数据挖掘类核心算法、基于图(graph)运算等应用作为评测。.2..在功率预算分配方面，提出了一系列基于博弈论或动态规划理论的优化方法，可以提升系统的整体效能。.3..在任务管理和迁移方面，提出了一系列基于branch and bound和启发式算法的碎片整理方法（defragmentation），用以优化任务之间的通信和能耗。.4..在片上网络通信路径规划上，提出了基于动态规划的路由算法，可以有效提升可靠性。