基于阻变存储器的NVSRAM存储系统研究

With the rapid growth of applications for wearable device, internet of things, cloud computing and big data, the normally-off computing technology has become the main means to solve the bottleneck of battery life for intelligent terminal; As the core component of SoC chip, the static random access memory (SRAM) has the disadvantage of data loss after power off. In order to meet the requirement of normally-off systems, the nonvolatile SRAM becomes the hotspot of research. RRAM has a strong competitive advantage in nonvolatile SRAM because of its good electrical characteristics, small area and better compatibility with CMOS process. This project will study the nonvolatile SRAM (NVSRAM) storage system based RRAM at the advanced technology. Considering the process variation, a set of design and evaluation methods for the nonvolatile SRAM high reliability storage unit is established. In order to ensure the reliability of the system operation, a high reliability control mechanism for NVSRAM system is constructed. Additionally, from the perspective of shortening the break even time (BET), the energy consumption model for the normally-off computering is also builded, which will provide theoretical guidance for the optimization of the design; Reash and design the nonvolatile SRAM memory chip with independent intellectual property rights to meet the needs of normally-off computing, which is far-reaching significance for the rapid development of our country's Internet of Things.

随着可穿戴设备、物联网、云计算及大数据应用的快速增长，常关断计算技术逐渐成为解决智能终端续航瓶颈的主体方向；而静态随机存储器作为SoC芯片的核心部件在掉电后存在数据丢失的缺陷，为满足常关断计算需求，非易失性SRAM成为研究的热点；RRAM因其良好的电学特性、面积小且与CMOS工艺良好兼容等特点在非易失性SRAM中表现出了很强的竞争优势。本项目将在先进工艺下对RRAM型非挥发性SRAM存储系统进行研究：在考虑工艺波动的基础上，建立一套适用于非挥发性SRAM高可靠性存储单元的设计及评估方法；构建适用于非挥发性SRAM系统的高可靠性控制机制，确保系统的可靠性操作；从缩短最佳盈亏时间的角度，建立面向常关断计算的非挥发性SRAM存储系统能耗模型，为系统优化设计提供理论指导；研发具有自主知识产权的非挥发性SRAM存储芯片，满足未来常关断计算需求，对我国物联网快速发展具有深远的意义。

随着可穿戴设备、物联网、云计算及大数据应用的快速增长，常关断计算技术逐渐成为解决智能终端续航瓶颈的主体方向；而静态随机存储器作为SoC芯片的核心部件在掉电后存在数据丢失的缺陷，为满足常关断计算需求，非易失性SRAM成为研究的热点；RRAM因其良好的电学特性、面积小且与CMOS工艺良好兼容等特点在非易失性SRAM中表现出了很强的竞争优势；本项目通过对高速高恢复率及低恢复功耗RRAM型存储单元结构、高可靠性关键控制电路、恢复率及功耗考量的NVSRAM存储系统架构研究，完成了对NVSRAM的系统研究。具体包括，以晶体管多次复用以节省面积损耗并提升性能为核心，提出了具有高写能力、高读稳定性及高数据恢复率且同时避免半选问题的新型平均7T1R存储单元电路（MS-7T1R）；并基于上述单元结构完成了单元可靠性评估、阵列设计、高可靠性控制电路设计、功耗及性能考量的整体存储系统架构设计。创造性的提出了“充电及反向恢复”技术，实现了整体系统高速及低功耗双模工作配置。项目完成了2KＸ32bit NVSRAM存储系统原型电路设计，仿真结果表明，设计的7T1R结构在低功耗模式下相较于传统6T SRAM的读静态噪声容限提高了154%，在高速模式下相较于传统6T SRAM的读速度提升了23%。且在较低电源电压下，与传统方案相比，所设计的NVSRAM系统数据恢复率具有明显提升，当电压小于0.95V时系统恢复率依然达到100%。通过项目研究，为研发具有自主知识产权的非挥发性SRAM存储芯片满足常关断计算需求提供了技术支撑，对我国物联网快速发展具有促进作用。