高密度高可靠性亚阈值静态存储器的理论研究

With the increasingly low power demand for wireless sensor networks and medical electronics, more and more researchers pay attention to low power technique for SRAM, as its power consumption dominates total chip power consumption. Aggressive voltage scaling to the subthreshold region helps achieving ultra-low power dissipation of 2-3 orders of magnitude lower power than conventional circuits. However, based on the contemporary circuit design theory, the subthreshold circuit would face the problems of low reliability and density, which would impede SRAM's practical applications. The purpose of the study is to develop a methodology for subthreshold SRAM design. There are four major parts contained in our research. First, a energy consumption model needs to be established to provide a general guidance for the subthreshold SRAM design; second, combined with structure innovation, partical dynamic threshold voltage adjustment scheme has been adopted to design high density and high reliability subthreshold bitcell; third, a new On-Off current ratio enhancement circuit has been proposed to address the problems caused by the reduced On-Off current ratio and enhance the reliability and density of SRAM array; forth, based on the hysteresis effect of the schmitt trigger, a universal circuit design scheme has been established to enhance the reliability of the interface circuits. With all these designs, a high density and high reliability subthreshold SRAM can be realized. At the same times, this research can get strong reference values for subthreshold logic design and it can also promote the design of FPGA based on SRAM into the subthreshold regime with profound significance.

随着无线传感网络和医疗电子为代表的应用背景对低功耗要求越来越高，能耗大户静态存储器（SRAM）的低功耗设计受到广泛关注。当电源电压降至器件亚阈值区，电路功耗可降低2到3个数量级，具有显著的低功耗优势。但依据常规电路设计理论，设计出的亚阈值电路存在可靠性和集成度受限问题，无法满足大容量SRAM技术指标。因此本项目研究亚阈值SRAM设计理论，构建能耗模型，为亚阈值SRAM设计提供理论指导；通过部分动态阈值电压调节技术与结构创新相结合的方法设计高密度高可靠存储单元；提出一种新颖的开关电流比增强方案，解决亚阈值器件开关电流比恶化导致的存储阵列密度和可靠性问题；借鉴施密特触发器"滞回"效应构建普适的亚阈值电路实现方案，增强接口电路可靠性；在上述基础上最终实现高密度高可靠亚阈值SRAM。该项目的最终成果，对亚阈值电路设计有很强的参考价值，并能推动基于SRAM的FPGA进入亚阈值区，具有深远的科学意义。

医疗芯片主要应用于可穿戴式、便携式、植入式医疗仪器中，超低能耗是其主要设计挑战。降低电源电压至MOS管亚阈值区域可以使得电路能耗比常规电路设计能耗节省大约一个数量级，因此亚阈值设计成为医疗芯片设计的主要趋势之一。需要注意的是，亚阈值设计具备与常规设计完全不同的电气特性，MOS管驱动电流与晶体管阈值电压的指数级关系使得常规的靠尺寸调节满足设计性能需求的方式已不再适用。存储体设计成为亚阈值设计的难点之一。同时，随着电源电压的降低，MOS晶体管的开启关断电流比（ ）急剧降低，泄漏功耗在总功耗中所占据的比重越来越大。本课题着重研究了低泄漏电流的亚阈值存储体。.本课题的工作包括：（1）通过分析亚阈值电路的延时模型、能耗模型，提出存储体最低和最优化电源电压的取值范围；（2）提出一款可以工作在亚阈值区域（200 mV电源电压）具有自适应泄漏电流切断机制的SRAM存储单元，该设计不仅能够从降低电源电压技术中获得总功耗的显著降低，还能够根据存储单元的操作状态自适应限制泄漏电流的消耗，进一步降低系统总功耗；（3）为保证设计良率，满足设计密度需求，本课题设计采用了以下几种电路技术：（a）利用施密特反相器作为亚阈值存储电路的接口电路，“净化”外部信号；（b）采用伪电流镜补偿技术与可写回的敏感放大器相配合的方法补偿存储体操作过程中的未选中存储单元的泄漏电流，增强亚阈值存储电路的存储密度；（c）通过阈值电压平衡机制，平衡PMOS和NMOS晶体管的阈值电压值显著提高整体设计的工艺偏差容忍度；（d）采用电容型电平转换器根据具体应用需求提升模块电源电压以扩展本设计的应用领域。.本课题设计的32×256 bits亚阈值存储电路采用130 nm工艺实现，整个芯片的面积为141.1 μm×352.6 μm。测试结果表明，本设计的电路在200 mV工作电压下工作频率可以达到138 kHz，总功耗为0.13 μW。与参考文献中的亚阈值SRAM存储单元相比，本课题设计的存储单元具备以下优点：（1）更好的工艺鲁棒性；（2）更低的泄漏电流。而与常规六管存储单元相比，本课题设计所消耗的功耗仅为常规六管存储单元功耗的1.16%。