应变Si组合发射区SOI SiGe HBT BiCMOS器件研究与设计

With the fast-growing markets in wireless communication, there is an increasing demand for low-power and high-performance microwave and millimeter-wave SiGe BiCMOS integrated circuits. The flexibility of the silicon-on-insulator (SOI) device architecture allows the obtaining of optimal electrical property for reduced parasitic capacitance, low leakage current, and improved immunity to substrate noise and crosstalk. The Strain technology is the effective way to improve carrier mobility, which has wide application in high-speed, high-performance semiconductor devices and integrated circuits. Significant change in band structure and carrier mobility enhancement of strained Si and Si1-xGex materials lead to the improvement of strained Si-based devices performance. Therefore, the performance of SiGe BiCMOS can be improved by adopting SOI technology and the strain technology. And the new SiGe BiCMOS unit is composed of strained Si combined emitter HBT and strained CMOS. In view of its originality and potential application, this project will systematically develop it from theoretical and experimental aspects. 1) Study the effect of strained Si layer in combinational emitter on the electrical characteristic of HBT device; 2) Analyze the change in the fundamental electrical parameters of the collector region in HBT device caused by SOI technology including the electric field, the potential and the depletion width, and discuss the influence of the fundamental electrical parameters on the subsequent critical parameters, such as parasitic resistance, parasitic capacitance, and the cut-off frequency qualitatively; 3) Reveal the relationship between structure and performance of strained CMOS and SOI substrate; 4) Optimize devices structure parameters and develop high performance strained Si combined emitter SOI HBT and SOI strained CMOS devices. 5) Verify the extent to BiCMOS performance improvement by the Inverter simulations. This project has therefore been able to make contributions in the performance improvement, development and application of BiCMOS integrated circuits..

本项目针对SiGe BiCMOS集成电路性能提升的应用需求，将SOI衬底技术及应变技术优势同时引入到SiGe BiCMOS工艺中，形成应变Si组合发射区HBT/应变CMOS全平面SOI BiCMOS器件。该器件结构新颖、性能增强，对其深入研究具有重要的理论意义和应用价值。为此，本项目重点研究应变Si组合发射区HBT器件发射区中应变Si层对HBT器件电学特性的影响；分析SOI衬底致HBT器件集电区基本电学参数的变化及其与核心参数的关系；揭示SOI衬底与应变CMOS器件结构和性能的关系；基于器件电学特性的分析，优化器件结构参数，设计出高性能的应变Si组合发射区SOI HBT及SOI BiCMOS器件结构；开展BiCMOS反相器仿真研究，验证BiCMOS性能提高的程度。通过以上研究，为BiCMOS集成电路性能的提高及应用奠定理论和实践基础。

本项目针对SiGe BiCMOS集成电路性能提升的应用需求，将SOI衬底技术及应变技术优势同时引入到SiGe BiCMOS工艺中，形成应变Si组合发射区HBT/应变CMOS S(G)OI BiCMOS器件。该器件结构新颖、性能比常规SiGe BICMOS增强，对其深入研究具有重要的理论意义和应用价值。为此，本项目重点研究了应变Si材料能带结构以及应变Si组合发射区HBT器件发射区中应变Si层对HBT器件电学特性的影响，分析了S(G)OI衬底HBT器件基本电学参数（放大系数、特征频率与击穿电压），设计了几种新型的S(G)OI应变Si/SiGe HBT结构与制造工艺，研究了SOI衬底与应变CMOS器件结构和性能的关系，基于器件电学特性的分析，设计出高性能的应变Si组合发射区SOI HBT及S(G)OI BiCMOS器件结构；开展CMOS反相器仿真研究，验证BiCMOS性能提高的程度。通过以上研究，为BiCMOS集成电路性能的提高及应用提供一定的理论和实践基础。