基于扩展控制数据流图的异构通用计算建模与性能评估

With the technological advancement of mobile internet, huge performance demanding has been noticed. However, traditional CPU architectures, which primarily focus on the low-latency execution, cannot fulfill those increasing demand on performance. The heterogeneous computing, which combine a Multi-Core CPU and massive computation elements (ALU array, in most cases), has been recognized as one of the promising solutions. However, since the lack of high-level hardware model as well as software programming model, the developers cannot evaluate and optimize the performance of proposed heterogeneous architecture quantitatively. In order to do full design space exploration and performance evaluation, we firstly extend the traditional control data flow graph (CDFG) to illustrate the microarchitecture of heterogeneous computing. Then, we employ the GPGPU to accelerate the optimization process of the proposed ECDFG. Lastly we remap the selected parameters of the microarchitecture to heterogeneous computing platform to fulfill the performance demanding of the applications.

随着移动互联网应用与服务的演进，巨大的计算需求开始释放。传统面向低延时的处理器设计已经无法满足应用对处理器计算性能的需求。CPU+计算阵列的异构通用计算模型通过对应用中控制密集型和数据密集型计算的切割与映射，可以提供50倍以上的加速比。然而目前异构通用计算由于缺乏统一的硬件高层模型与软件编程模型，难以开展大规模的设计空间探索。本研究拟通过改造传统的控制数据流图，加入异构计算引擎微结构信息，从而获得扩展了微架构信息的控制数据流图（ECDFG）。然后借助GPGPU方式对该图进行切割和优化，间接实现对异构通用计算资源的分配与设计空间探索，最终得到优化后的系统硬件微结构，从而完成面向某一类（或某几类）应用领域的软硬件协同设计与性能评估。

随着移动互联网应用与服务的演进，先进的嵌入式SoC开始集成越来越多异构的计算以及分布式的片上存储资源。传统面向实时控制设计的通用处理器核已经无法满足移动智能终端应用对处理器计算性能的需求。CPU+计算阵列的异构通用计算模型通过对应用中控制密集型和数据密集型计算的切割与映射，可以提供较为显著的加速比。然而目前异构通用计算由于缺乏统一的硬件高层模型与软件编程模型，难以开展大规模的设计空间探索。本研究拟通过改造传统的控制数据流图，加入异构计算引擎微结构信息，从而获得扩展了微架构信息的控制数据流图（ECDFG）。然后借助通过修改传统的图切割与优化，使之可以处理带有微结构参数的流图节点，间接实现对异构通用计算资源的分配与设计空间探索，最终得到优化后的系统硬件微结构，从而完成面向某一类（或某几类）应用领域的软硬件协同设计与性能评估。