簇内紧耦合的高可靠适应性众核处理器体系结构研究

Manycore processors are quickly becoming dominant architectures, driven by shrinking process and diminishing returns from additional per-core complexity. As device feature size continues to shrink, reliability becomes a severe issue due to process variation, particle-induced transient errors and transistor wear-out/stress such as the Negative Bias Temperature Instability (NBTI) that affects system life-span. Traditional fault tolerant strategies of processors can no longer meet the demand because most of them only focus on soft errors. This project proposes a new manycore architecture named Highly Reliable Adaptive Manycore Architecture Based on Tightly Coupled within-Cluster Cores, which can run in two modes- highly reliable mode and high performance mode. In highly reliable mode, within-cluster cores are tightly coupled through shared L1 cache. A main core detects errors through dual-pipeline execution, while a backup core copies the execution environment of the main core. When an error is detected, the task will be transferred to the backup core quickly, which can reduce impact on system performance. With L1 Cache management, highly reliable manycore processors can also be used for high performance..This project will focus on the following problems: (1) The granularity of the tightly coupled cores at the consideration of reliability and performance need. (2) The impact on performance and power, etc. which caused by stride length for execution environment synchronization between main core and backup core. (3) Unified L1 Cache scheduling mechanism based on tightly coupled within-cluster cores. (4) The scheduling mechanism for manycore management. The research results will help to expand the application scope of highly reliable manycore processors.

众核处理器将成为未来电子系统中的核心，随着工艺尺寸减小、电压降低及工艺的不稳定性，器件的可靠性问题日益严重。传统的处理器可靠性只考虑软故障的容错策略已不能满足需求。本项目提出一种新型的簇内紧耦合的高可靠适应性众核体系结构，旨在从处理器的高可靠性出发，在高可靠执行模式下采用簇内的核通过共享L1 Cache进行紧耦合，核内采用流水线级的冗余执行进行错误检测，采用专用的备份核动态备份主执行核的执行现场，以便在发生故障时任务快速迁移到备份核执行，降低对系统性能的影响。同时通过对L1 Cache的管理，使高可靠众核处理器在普通场合具有较高性能。.本项目将研究综合考虑可靠性和高性能需求的紧耦合的粒度、主执行核和备份核的现场同步步长与性能和功耗等开销的表征、簇内紧耦合的适应性众核架构下统一L1 Cache调度机制以及容错众核处理器的执行核管理机制等问题。研究成果将有助于拓展高可靠众核处理器的应用范围。

随着工艺尺寸减小、电压降低及工艺的不稳定性，器件的可靠性问题日益严重，这将严重影响众核处理器的可靠性。本项目提出了一种新型的簇内紧耦合的高可靠适应性众核体系结构，开展了应用于处理器中的新型存储器件在微体系结构级的可靠性研究。主要成果如下：.1.提出了簇内紧耦合的高可靠适应性众核体系结构，该结构可针对应用的需求在高可靠模式和高性能模式灵活切换工作，基于该结构，可一步研究紧耦合的粒度方面进行优化选择、主执行核和备份核之间执行现场同步步长与性能、功耗等开销的表征、簇内紧耦合的适应性众核架构下统一L1 Cache调度机制和容错众核处理器的执行核管理等问题。.2.针对众核处理器LLC的候选器件STT-RAM的读写不对称问题，提出了一种非对称写通道模型（AWC）和基于该模型的内容相关的ECC（CD-ECC）方法来减小cache中数据块的海明距离。CD-ECC中对典型情况下和最恶劣情况下的数据分别进行考虑，采用不同的编解码方法。与蒙特-卡洛模拟方法相比，AWC的精确性与其相当，但是仿真时间大大减少。基于AWC的CD-ECC方法有效地提高了cache行的可靠性。仿真结果显示，与传统的ECC相比，CD-ECC可以将仿真的计算机系统的可靠性提高10至30倍，硬件开销和性能开销仅有0.5%。 .3.针对用作LLC的MLC STT-RAM的访问延迟要大于SLC可能会抵消掉容量增加带来的增益问题，提出了反向连接的MLC STT-RAM的单元结构，基于该结构目提出了一种自适应程序要求的体系结构级解决方案。即在体系结构级，利用单元分割映射技术将Cache块分成“软路”和“硬路”，“软路”的访问速度更快。还研究了用来确保绝大多数Cache访问出现在“软路”上的Cache块迁移技术。相应的“程序可感知”加速技术使得应用程序可以根据自身行为适时调整Cache速度和容量。仿真结果显示综合应用这些技术后，系统性能可以平均提高10.3%，同时L2 cache的动态能耗可以降低26.0%。.4.针对可能在众核处理器系统中大量应用的NAND FALSH的有限次写操作导致的寿命问题，本项目提出了一种数据图案感知的寿命延迟技术（DPA）来处理存入存储单元的逻辑1和逻辑0的比例。实验结果显示，DPA能把NAND flash的寿命延长3或4倍，而性能开销大约是13%。