面向PVT波动的超低电压宽脉冲锁存器电路设计方法研究

With the rapid growth of applications such as wireless sensor network, plantable medical electronics and internet of things (IoT), the studies on energy-efficient ultra-low-voltage circuits design techniques become more interested. The process-, voltage- and temperature- (PVT) variations are one of the key challenges in ultra-low voltage circuit, which seriously affect the performance, function and energy efficiency of the circuit. The goal of this proposal is focused on tolerance of PVT variations, high performance and energy efficient design methodology of wide-pulsed-latch circuit under ultra-low voltage. The research contents of this proposal include: 1) Design methodology of many-Vt delay cells under the inverse narrow width effect, design techniques of many-Vt delay cells with nano-meter technologies, and the short path padding techniques based on many-Vt delay cells; 2) Timing Error Detection and Correction (EDAC) mechanism based on the resilient timing constraint, the robust EDAC circuit structures and EDAC circuit insertion techniques; 3) Design principle and techniques of wide-pulsed-latch and register -based hybrid circuits. The design methodology of wide-pulsed-latch based circuits with tolerance of PVT variations under the ultra-low voltage will be proposed. Accordingly, the design flow of wide-pulsed -latch based circuits will be established. Finally, 2~3 prototypes of ultra-low voltage circuit chip with EDAC ability will be developed. And then, we will measure and verify the advantages of wide-pulsed-latch based circuits in their reliability, performance and energy efficiency. As a result, the outcome this research work will promote the development of wide-pulsed-latch based circuits with tolerance of PVT variations.

随着无线传感网、植入式医疗电子和物联网等应用的不断涌现，基于超低电压的高能效电路技术不断受到人们的关注。在超低电压下，工艺、电压和温度的波动及其影响是当前电路设计面临的最大挑战之一。本项目以宽脉冲锁存器电路为研究对象，以提升超低电压下电路抗PVT波动的能力、电路性能和电路能效为目标，通过研究基于反向窄沟道效应的众阈值延迟单元的设计方法、众阈值延迟单元电路设计技术和基于众阈值延迟单元的短路径填充技术，基于弹性时序约束的电路时序错误检测与校正机制及其单元电路结构、错误检测与校正单元插入技术，基于宽脉冲锁存器和寄存器的混合电路设计等方法和技术，提出面向超低电压下抗PVT波动的宽脉冲锁存器电路设计方法，建立相应的电路设计流程，开发2~3款含时序错误检测与校正功能的超低电压电路芯片原型，验证宽脉冲锁存电路在可靠性、性能和能效上的优势，从而推动基于宽脉冲锁存器的抗PVT波动电路技术的发展。

随着无线传感网、植入式医疗电子和物联网等应用的快速发展，基于低电压的超低功耗高能效电路设计技术受到了广泛关注。本项目以宽脉冲锁存器电路为研究对象，以提升超低电压下电路抗PVT波动的能力、电路性能和电路能效为目标，重点研究了众阈值延迟单元电路和众阈值逻辑单元库设计技术、新型的电路时序错误检测与校正电路技术、基于50%占空比的宽脉冲锁存器处理器和多相锁存器深度流水线电路技术、面向多电压/时钟域的超低电压NoC和新型存储器设计技术等内容，设计了3款超低电压芯片原型，验证了基于宽脉冲锁存器流水线在处理器、深度流水线加速器上的性能和能效上优势，发表包括ISSCC、JSSC、DAC、IEEE TCAS-I和TCAS-II在内的论文17篇，申请发明专利6项、授权3项。