硅基铌酸锂铁电单晶薄膜导电畴壁存储机理及Crossbar阵列集成研究

At present, commercial ferroelectric memories, which has the advantages of fast reading and writing speed, low power consumption and non-volatile storage, limited by the destructive readout technology of charge integration, therefore the storage density does not exceed 8 Mb. This project is based on the ferroelectric domain wall memory, which adopts non-destructive readout current technology with independent innovation and breaks through the bottleneck of high-density development. By applying an in-plane write electric field, rewritable conductive domain walls are formed and the domain logic information with current can be read out in the nano-scale memory cell. The project will choose lithium niobate single crystal materials, conquer the key technologies such as memory cell consistency and process stability and finally, develop integrated demo chips of ferroelectric domain wall memory in the laboratory. The interface passivation layer forms between the ferroelectric memory cell and the electrode, which has the natural unidirectional conductivity. The on-off current ratio is greater than 10^5, which satisfies the requirement of crossbar interconnection. Influence of quantum tunneling effect on the off-state current can be studied in small-size memory cells and advanced nano-machining technology can be explored to improve the switching current ratio. The formation mechanism of ferroelectric domain surface passivation layer will be researched to reduce the turn-on voltage of domain wall current. In addition, the memory cells can be stacked in three-dimension on the Si-based circuit substrate, the storage density can be comparable to the non-volatile flash memory (NAND), and the reading and writing speed of this memory is in nanosecond. It provides theoretical support for high-density memory technology with independent intellectual property rights in China.

目前商业铁电存储器采用电荷积分的破坏性读出技术，具有读写速度快、抗辐照、低功耗和非挥发性存储等优点，但是存储密度不超过8Mb。本项目基于本人所发明的铁电畴壁存储器，运用电流读出技术，突破高密度发展的瓶颈。通过施加一个面内写电场，产生可擦写的导电畴壁，能够非破坏性地读出纳米存储单元中电畴逻辑信息；采用铌酸锂单晶，突破存储单元一致性和工艺稳定性等关键技术，在实验室内集成铁电畴壁存储验证芯片，且铁电存储单元与电极接触处形成界面层，具有天然的选择管特性，满足交叉棒（Crossbar）互联的要求，开关电流比大于10^5。分析小尺寸存储单元中量子隧穿效应对关态电流的影响，提高开关电流比；研究铁电畴表面钝化层形成机制，降低产生畴壁电流的开启电压。实现存储单元在Si基电路上三维堆垛，存储密度可以和非挥发闪存(NAND)相竞争，且具备纳秒量级读写速度，为我国具备自主知识产权的高密度存储器技术提供理论支持。

铁电畴壁存储是基于铁电极化调控畴壁电导新原理，即电场诱导铁电畴翻转调控畴壁（畴壁的电导率远大于绝缘铁电材料）产生或消失作为非挥发性存储器的开关状态，是一种具备高密度、高速读写、低功耗、高可靠性的非易失性存储器，其工作原理有别于传统电荷积分读取信息的铁电存储器，突破了目前已商业化铁电存储器存储单元无法缩小和信息破坏性读取的瓶颈问题，有望突破“存储墙”限制，使计算机整体性能成百倍或千倍地提升。本项目基于铌酸锂铁电单晶材料，通过优化制备工艺和电子束曝光技术，同时引入“黑化”工艺和电极粘附层Cr进一步优化铁电表面层和电极接触，首次制备出最小可达15nm的存储单元。实现了4×4、8×8等多种集成规模的Crossbar阵列，首次在阵列中验证了畴壁存储单元在读写时不需要额外制备选择管也可以防止相邻存储单元间串扰(cross-talk)。通过改变左右电极的间距，实现开启电压Von在0和8.7V之间的连续调制，从而为Crossbar结构的存储器件提供了较宽的写入和读取电压窗口。通过设计铌酸锂器件结构是存储单元具备低电流写入的低功耗要求和高电流读出的高速信息读取要求。通过对器件表面层的减薄实现了畴壁与金属近欧姆接触，使畴壁存储单元具备忆阻器的功能，可应用于信息的多位存储和类神经模拟机器深度学习等领域。在存储单元基础上，发明了非易失铁电畴壁场效应晶体管，可进行非易失逻辑运算，实现存算一体化功能。在Nature Communications，Advanced Function Materials，Advanced Electronic Materials，IEEE Electron Device Letters等国际知名刊物发表论文18篇。获授权发明专利3项，另申请5项。协助培养课题组硕博研究生6人。