纳米FinFET器件的统计涨落效应和电路仿真模型研究

With the CMOS downscaling into nanoscale technology node,the conventional planar MOSFET can no longer meet the requirements of high-performance nanoscale integreted circuits due to severe short channel effects. In order to obtain better gate control characteristics of devices, non-conventional device structures such as FinFET and surrounding-gate MOSFET were proposed. However, compared with the planar device structure, non-conventional nanoscale transistors are less immune to the process fluctuation.Therefore, this project aims to research the impact of the statistical process fluctuation on nanoscale FinFET device and circuit performance. First, the relation between process fluctuation and device performance parameters is studied and a reliability model is established based on the physical model of FinFET. Sencond, the key device parameters of nanoscale FinFET are extracted, the dependence of which on the process fluctuation is also investigated. Based on our proposed reliability model, Monte Carlo simulations are carried out and compared with numerical simulation results. Finally, the reliability model for the process variation is verified and calibrated by comparing with the experimental data. With the purposes of developing a model with process sensitive parameters and predicting the performance of nanoscale FinFET devices and circuits under process fluctuation, this proposed project will help improve the optimization of FinFET device and reduce the impact of process fluctuation on circuit design.

随着CMOS尺寸进入纳米级，短沟效应导致传统的平面晶体管退化,而使其不能满足高性能纳米集成电路的要求。为了获得更好的开关控制特性，非传统结构如FinFET，环栅MOSFET等被提出。 然而，与传统平面结构晶体管相比，非传统纳米晶体管由于更小的尺寸和更低的沟道掺杂，更容易受到工艺涨落的影响。因此，本项目将研究工艺统计涨落对纳米FinFET器件和电路性能的影响。首先，在纳米FinFET器件物理模型的基础上，建立工艺涨落与器件性能参量之间关系。然后，对纳米FinFET器件的关键参数进行提取，研究工艺涨落对关键参数的影响。采用建立的模型进行模拟，并与数值模拟器结果对比，最后用实验数据对工艺涨落模型进行验证和调试。本项目将建立包含工艺敏感度参数的纳米FinFET电路仿真模型，实现对纳米FinFET工艺涨落的预测，有助于新型FinFET器件结构优化和减少工艺涨落对电路设计的影响

随着CMOS尺寸进入纳米级，短沟效应导致传统的平面晶体管退化而使其不能满足高性能纳米集成电路的要求。为了获得更好的开关控制特性，非传统结构如FinFET，环栅MOSFET等被提出。 然而，与传统平面结构晶体管相比，非传统纳米晶体管由于更小的尺寸和更低的沟道掺杂，更容易受到工艺涨落的影响。因此，本项目研究工艺统计涨落对纳米FinFET器件和电路性能的影响。首先，在纳米FinFET器件物理模型的基础上，建立工艺涨落与器件性能参量之间关系。然后，对纳米FinFET器件的关键参数进行提取，研究工艺涨落对关键参数的影响。采用建立的模型进行模拟，并与数值模拟器结果对比，最后用实验数据对工艺涨落模型进行验证和调试。本项目建立包含工艺敏感度参数的纳米FinFET器件和电路模型，实现对纳米FinFET工艺涨落的预测，有助于进行新型FinFET器件结构优化和减少该效应对电路设计影响。