GPGPU访存系统中共享资源管理和调度的关键技术研究

GPGPUs have been becoming essential components in various computing systems for application acceleration. However, high thread-level parallelism (TLP) and increasing number of GPGPUs in system would cause contention in the limited shared resources of GPGPU memory sub-system, negating acceleration performance. Therefore, in this proposal, a set of management methods and scheduling policies towards shared resources in GPGPU memory sub-system are proposed at different architectural levels for contention reduction and further performance improvement. Specifically, we will conduct this research in three aspects: 1) leveraging the characteristic of different thread organizing granularity in an SIMT core to support thread throttling and cache bypassing for reduction in L1 data cache thrashing, 2) exploiting distinction of memory access behavior and latency among different SIMT cores for resource allocation of L2 data cache and memory request scheduling in memory controllers, and finally 3) reducing overhead of remote memory access based on a unified memory semantic on- and off-chip interconnect between CPU and GPU in the multi-GPGPU architecture, and implementing a special scheduler that is aware of the disparity between local and remote memory requests. By means of experiments based on system-level software simulator and FPGA prototype of key hardware modules, research contents of this proposal can be effectively verified and evaluated. In the end of this project, three to five high-quality and SCI/EI-indexed papers will be published; and four to five patents will be applied as well.

GPGPU已成为多种计算系统中不可或缺的重要加速部件。然而，较高的线程级并行性以及系统中越发增加的GPGPU数量会竞争使用访存系统中各类有限的共享硬件资源，严重影响加速性能。针对上述问题，本课题拟从不同体系结构层次，对GPGPU访存系统共享资源的管理方法及调度策略展开研究，减少资源竞争的情况，进一步提升GPGPU处理性能，具体包括三个方面的研究工作：1）在SIMT处理器内部针对不同线程组织粒度的特点，进行活跃线程限制和缓存旁路，减少L1数据缓存抖动；2）在进行L2缓存资源分配和内存控制器请求调度时，考虑不同SIMT处理器的访存特征及延时差异；3）在多GPGPU系统中使用基于内存语义的统一片内-片间互连，降低远程访存开销，同时根据本地和远程访存请求的差异进行调度。通过软件模拟器评估及关键模块FPGA原型测试，验证上述研究内容。本课题拟发表3-5篇SCI/EI检索论文，并申请4-5项专利。

以GPGPU和FPGA为代表的异构加速计算资源已成为众多计算系统中必不可少的组成部分。然而，数量不断增长的异构加速处理单元（如GPGPU的SIMT处理器）会竞争使用访存系统中各类有限的共享硬件资源，影响加速处理性能。课题通过三年的研究，在以下方面取得创新成果：1）面向典型应用场景，设计并实现一种可在异构加速处理单元中使用的新型访存单元，支持高并发、乱序和异步的内存访问接口，随机访存性能最高提升3.5倍，相关成果在国防科技大学学报发表。2）聚焦异构加速资源在内存竞争访问中面临的性能和功耗问题，实现一种穿梭片上网络架构，通过可重构链路模块和路由调度策略，平衡不同异构加速处理单元访存带宽，并降低整体访存功耗，相关成果在IEEE TCAD期刊发表。3）提出并设计一种新型定制内存语义互连及相应的共享访问机制，支持延时< 2μs的异构加速资源多节点环境下的跨节点内存访问，实现可支持细粒度数据交互的异构计算资源池化。4）关注异构加速资源云化趋势，践行“科研重工业”模式，提出一种基于标准以太网互连的新型异构加速计算云服务器体系结构并自主研发原型系统，已累计服务超过300名学生开展计算机硬件系统类课程科研教学实践；相关研究成果在国际计算机教学领域旗舰会议ACM SIGCSE发表，是该会议50年历史上国内第四篇全文论文。