沟道工艺偏差对亚10纳米无结FinFET输运效率的影响及机理研究

FinFET will replace the conventional bulk MOSFETs to be dominant in the continued device scaling. However, the electron delocalization of dopant atoms is observed in a few nanometers scale that becomes a great challenge to form the abrupt junctions as the device size shrunk to deep-nano level. The Juncitonless FinFET, with the same doping type and concentration of the source/drain and channel, is proposed to overcome this limitation and continue the device scaling below 7 nm. It has also been found that the junctionless device has good subthreshold characteristics and superior ability to suppress short channel effects as compared with the conventional inversion-mode transistor. Hence, it is recognized as the promising candidates of the next generation element device in the integrated circuits. Whereas the drive capability of junctionless FinFET still need to be improved due to the high doping concentration, which is mainly affected by the carrier transport efficiency as the carrier is under quasi-ballistic transport. On the other hand, the channel process variation for the device, such as line edge roughness and Fin vertical nonuniformity, is inevitable during the fabrication. A quantum simulator is thus developed based on sp3d5s* the tight-binding method, the real space of non-equilibrium Green's function transport theory and three-dimensional Poisson’s equation in this work, which is utilized to study the carrier transport efficiency of sub-10 nm junctionless FinFET with channel process variation. Its impact and physical mechanism are fully carried out. Then the physical association between the carrier transport efficiency with the narrowest channel, impurity scattering, electrostatic properties and quantum effect is investigated from atomic scope. The Monte Carlo method is also incorporated into simulator for analyzing the impact of carrier traversing distance on transport efficiency and the energy transfer is further added to study the gate tunneling and bipolar effect through the energy spectrum and density of states. Finally the device structure of junctionless FinFET is optimized to suppress the gate tunneling and bipolar effect. Through this work, the results will provide an effective guide and generate an analytical method for enhancing the current drive capability of junctionless FinFET, which is helpful for its industrial application.

无结FinFET器件拥有优越的亚阈值特性和短沟道效应抑制能力，是有潜力缩进到7纳米以下的新一代器件结构。准弹道机制下，载流子输运效率成为改善器件电流驱动能力的关键。针对不可避免的器件沟道工艺偏差，本项目搭建基于sp3d5s*紧束缚方法、实空间非平衡态格林函数输运理论和三维泊松方程的全量子模拟器，开展其对亚10纳米无结FinFET载流子输运效率的影响及物理机理研究。从原子层次探讨载流子输运效率与沟道最窄处属性、杂质散射、区域静电特性及量子效应的物理关联。引入蒙特卡洛方法，分析载流子遍历距离对输运效率的影响。采用能量转移表征沟道工艺偏差对载流子隧穿几率的作用，深入能谱、态密度分析二级效应物理机理。本项目研究将优化无结FinFET器件结构，抑制二级效应，为提升无结FinFET电流驱动能力提供理论指导和分析手段，奠定无结FinFET器件工业化应用的基础。

无结器件作为有潜力缩进到7纳米以下的新型器件结构，需要进一步研究器件载流子输运机理，改善器件电流特性以及对抗工艺偏差的影响，但目前缺乏有效的仿真工具和集约模型。因此，本项目搭建了全量子三维器件特性模拟器，开展了对无结器件载流子输运机理、模型、结构优化等诸多方面的研究，主要完成了以下几个方面的研究内容：.1）亚10 纳米无结环栅器件载流子输运研究。基于sp3d5s*紧束缚方法构建硅纳米线的电子能带特性，并结合非平衡态格林函数输运和泊松方程建立器件的三维数值仿真模拟器，研究了亚10 纳米无结环栅器件极限特性和载流子输运机理，并详细分析了纳米线晶向、尺寸、spacer介电常数、参数波动和能级分裂对无结器件特性的影响。.2）无结器件模型研究。针对10纳米以上尺度的长短沟道无结器件，建立了一套集约SPICE电学模型，实现了基于无结器件的电路仿真，并开发了无结器件特性的在线仿真功能，提供给全世界研究人员使用。开发方法成功应用到Tunneling FET模型研究中。.3）工艺波动对无结器件特性的影响及抑制研究。开展了工艺偏差对双栅、Recessed gate等新型无结器件特性的影响，同时，针对无结器件特殊的体导通性质和工艺波动的影响，引入charge-plasma结构，优化无结器件性能并抑制线边缘粗糙LER的影响。.本项目研究为无结器件走向应用提供了一套实用的电路仿真模型，并为抑制工艺波动提供了解决思路和结构优化方案，同时模拟器的发展为后续的新结构、新材料器件研究提供了一个强有力的工具，帮助无结器件继续按比例缩小。