基于动态匹配的高能量利用率多层堆叠结构静态随机存储器（SRAM）关键技术

The increase of scale and integration of SRAM has brought the growth of power consumption. Reduce the operating voltage of SRAM is one of the effective methods to reduce the power consumption. Normally, there needs a DC-DC converter to realize the output voltage regulating, while the DC-DC converter will consume part of energy at the same time, which lower the energy usage efficiency of SRAM. In this project, the resistive subdivision technique is employed in the design of SRAM. By changing the series and parallel structures of equivalent resistance of SRAM cell, it realizes the adjusting of the SRAM operating voltage. The research work will based on to realize the key technology and implementation methods of dynamic matching high energy utilization efficiency multi-stack SRAM array structure, to solve the problem of the energy efficiency of SRAM. The study can guarantee high performance and low power consumption, and can also greatly improve the energy usage efficiency of SRAM. It will adapt to the requirements for the self-supply iot and embedded system applications, which have the quite demanding of power consumption. Compared with the previous SRAM array structure and power management design and manufacturing, this research has significant innovations. The research work meets the urgent requirements of the ultra low power integrated system, and has important theoretical significance and especially valuable in practical applications.

静态随机存储器（Static Random Access Memory，SRAM）规模和集成度的增加带来了功耗的增长，降低SRAM工作电压是减小其功耗的有效方法，通常需要DC-DC变换器来实现电压转换，但变换器在实现调压的同时又会消耗一部分能量，降低了SRAM阵列对电源能量的利用效率。本项目将电阻分压技术运用到SRAM设计中，通过改变SRAM单元等效电阻的串并联结构来实现对单元工作电压的调整，研究基于动态匹配的高能量利用率多层堆叠结构SRAM的关键技术和实现方案，解决SRAM的能量利用效率问题。本项研究可以保证SRAM的高性能并降低其功耗，同时还可大幅提高SRAM对电源能量的利用效率，适应对功耗要求非常苛刻的自供电物联网和植入式系统的应用。这对以往的SRAM阵列结构及电源管理的设计与制造而言，均具有创新意义。研究内容满足超低功耗集成系统的迫切需求，具有重要的理论意义和广泛的实际应用价值。

降低数字电路的工作电压是减小其功耗的有效方法，尤其是将工作电压降低至器件的亚阈值区间，这时将会达到最低能耗点，能耗显著下降。但是，过低的工作电压将会给DC-DC变换器的设计带来挑战，这是因为DC-DC变换器在过大的变压比下通常效率都不会高。针对这一问题，本项目提出并论证了一种堆叠数字单元结构，以提升其整体的工作电压，从而摆脱传统DC-DC变换器的束缚，提高数字单元对电源能量的充分利用。该数字单元以SRAM为基础，设计并实现了多层堆叠SRAM阵列及其与之匹配的辅助开关电容变换器结构，以实现超低功耗的同时提升电源能量的利用效率。同时，当等效阻抗不匹配时，除了采用辅助开关电容变换器进行调节外，该堆叠结构还可以实现自恢复。最后，通过采用标准0.18 μm CMOS 工艺，设计完成了一个4层堆叠的SRAM阵列结构，并且对辅助开关电容变换器按照平均电流10%的调整量进行设计。每层单元在450mV的工作电压下，各堆叠层电压精度达到99%，整个系统对电源能量的利用效率达到94%。