基于三维SoP的高性能微处理器片上互连和存储研究

The technology of high-performance microprocessors is an important foundation for national security and defense security. This project is aiming at the next generation mainstream architecture of the high-performance microprocessors in future ten to fifteen years. We will study the architecture of three dimensions (3D) optical interconnection network for the high-performance microprocessors based on System-on-Package (SoP) technology, the Network Calculus based analytical model and optimization method for the 3D interconnection network, and the on-chip 3D memory partition mechanism. There are three key scientific issues we will solve. Firstly, the multi-object optimization problem arisen from the design of high performance microprocessors interconnects, considering the power dissipation, bandwidth, chip area, reliability and so on. Secondly, the Network Calculus based conflict modeling technology introduced by the multi-traffic competing for network resource. Thirdly, the sensing mechanism of application program's memory access behavior. The features and innovations of the project include the on-chip 3D optical-electronic hybrid interconnection architecture, the conflict-tree calculus model of the multi-traffic competing for network resource and the high-precision predication model of the memory fault. In this project, We will propose an optical-electronic hybrid, double layer on-chip interconnection architecture, the Network Calculus based analysis and optimization mechanism of 3D on-chip interconnects, a 3D shared memory partition mechanism based on the memory access behavior model and the dynamic temperature model, and a high-precision, low dissipation dynamic fault-tolerance mechanism for 3D on-chip memory.

高性能微处理器技术是国家安全和国防安全的重要基础技术。本项目针对未来10-15年高性能微处理器的下一代主流体系结构开展研究，研究基于SoP的高性能微处理器的片上三维光互连体系结构、基于网络演算的三维互连结构性能分析与优化和三维片上存储划分机制等。要解决的关键科学问题是高性能微处理器互连结构中功耗、带宽、延迟、面积、可靠性等综合性能的影响因子调整方法问题、基于网络演算的三维片上网络多个业务流竞争网络资源的复杂冲突建模问题和用户程序的访存行为模式的感知机制三个问题。项目的特色和创新包括片上三维光互连网络的光电并行体系结构、多业务流竞争网络资源的冲突树演算模型和应用对片上存储失效的高准确性预测模型。项目将提出片上光互连网络的光电并行双层体系结构，提出基于网络演算的三维片上网络性能分析和优化方法、提出基于访存行为模型和动态温度模型的三维共享存储划分机制和提出高可靠低开销的三维片上存储动态容错机制。

本项目针对未来高性能微处理器的下一代主流体系结构展开研究，提出了软件定义的三维片上光网络SD-PNoC、基于蝶型结构的三维片上光网络SuP以及多层次混合的三维片上光网络HaoDo；基于网络演算理论对三维片上网络进行了性能分析，提出了高能效的片上网络PNC设计方法；提出了一种综合考虑温度、功耗和可靠性等因素的三维缓存结构SubCacheline；针对三维SoP设计中TSV的结构特点，对方形和圆形TSV在不同位置、结构的情况下进行了热建模；构建了对TSV结构进行模拟的3D-ICE模拟器，对模拟器的正确性进行了分析验证，并分析了TSV在不同布局、数量、大小时对三维集成电路的影响；利用3D-ICE模拟器分析了三维SoP的散热特点，并从静态、动态两个方面提出了适用于微通道液体冷却的三维微处理器的温度调节方案。项目研究期间，发表学术论文15篇，其中SCI检索5篇、EI检索3篇；撰写学术专著1部；申请发明专利6项；培养毕业博士研究生3人、硕士研究生6人。本项目的部分研究成果已成功应用于国防科学技术大学计算机学院自主研制的高性能多核处理器中。