SiC MOS栅介质与沟道界面态调控的机理与方法研究

SiC MOSFET is one of the most important power switching devices, and it is the key component for high efficient power module and power system application. The high density of interface trapping states at and near the interface between gate dielectrics and conducting channel is the dominant factor limiting channel carrier transportation and causing device stability problem. Efficient passivation of the interfacial charge trapping, engineering the interfaces and availability of stable gate dielectrics are the keys for SiC MOSFET device development. This project would study the effects of different interface engineering methods on device performance and stability, employing CV measurement with varied temperature, low temperature conductance method and stability tests. The targets are correctly characterization of charge trappings densities and distributions, including fast states, near interface electron/hole trappings, traps in the dielectrics and at the interface; modeling distribution characterization of SiC MOS interfacial states; illustration of mechanisms of different types of charge trapping on device performance and revealing the correlation between the charge traps and the device electrical performance, such as channel carrier transportation, threshold voltage shift, etc. This will support development of high performance and high reliable gate oxide techniques in the term of theoretical and technical guidance. The achievements of practical gate oxide techniques will surely have great application values and economic benefits for SiC MOSFET products.

SiC MOSFET是最重要的功率开关器件之一，是实现高效SiC功率模块与系统应用的关键；SiC MOS栅介质与沟道处的高界面态是限制沟道载流子传输和影响器件稳定性的主要因素，如何有效钝化界面电荷陷阱，调控界面态并实现高稳定性栅介质是SiC MOSFET器件开发的核心。本项目拟针对SiC MOS的不同界面态调控工艺及对器件稳定性和可靠性的影响，结合变温CV、低温电导法和可靠性试验等表征方法，实现对界面快态、近界面电子/空穴陷阱、介质和界面电荷陷阱密度和分布的准确表征；建立相应SiC MOS界面态陷阱分布特征模型，明确不同类型电荷陷阱对器件特性的影响机制，揭示电荷陷阱与器件电特性（沟道载流子输运、阈值电压漂移等）之间的联系，为开发高性能、高可靠SiC MOSFET栅氧工艺提供重要理论和技术支撑。本项目研究成果将开发实用化栅氧工艺，对SiC MOSFET产品开发具有重要应用价值和经济价值。

SiC MOSFET是最重要的功率开关器件之一，是实现高效SiC功率模块与系统应用的关键；SiC MOS栅介质与沟道处的高界面态是限制沟道载流子传输和影响器件稳定性的主要因素，如何有效钝化界面电荷陷阱，调控界面态并实现高稳定性栅介质是SiC MOSFET器件开发的核心。通过本项目的实施，在SiC MOS 的不同界面态调控工艺及对器件稳定性和可靠性的影响中，明确了界面快态、近界面电子/空穴陷阱、介质和界面电荷陷阱密度和分布的形成机制，准确采用变温CV、低温电导法和可靠性试验等表征方法进行表征；并对N2、Ar和电子注入，及微波等离子体氧化等不同调控工艺对SiC MOS界面的调控结果和机制进行了详细研究，为开发高性能、高可靠的SiC MOSFET 的栅氧工艺提供了重要的理论和技术支撑。