基于3-D EFD方法发展适用于传统及TSV技术的互连系统寄生电容模型研究

With rapid development of ultra large scale integrated circuits (ULSI) technology, the extraction of parasitic capacitances, which is essential in the analysis of CMOS circuits, becomes more and more difficult. First of all, it is increasingly challenging to extract the capacitances from back-end-of-line (BEOL) interconnect structures with ever shrinking sizes and modern technologies. Second, the 3-D through silicon via (TSV) technology, which is used extensively in 3-D integrated circuits, typically has complex structures, which is difficult to analyze its parasitic capacitance. The most importantly, the traditional modeling method of empirical fitting poses a formidable hurdle to develop a universal model for common CMOS interconnect and TSV interconnect. To solve the above issues in CMOS technology, we propose the project of "parasitic capacitance modeling of CMOS interconnect including traditional and TSV based on 3-D EFD method". The proposal target is to build compact capacitance models for both traditional BEOL interconnect and 3-D TSV interconnect, based on the analyzing of the electric field decomposition (EFD) between metal structures. The proposed model should be able to calculate parasitic capacitances for advanced interconnect structures, such as the copper diffusion resist layer and air gap technology, and different structures of TSV technology. It should also be easily embedded into different circuit simulation systems. With the newly developed models, we can then realize circuit design optimization in two to three years.

随着超大规模集成电路制造进入亚45纳米时代，寄生电容对电路性能的影响问题越来越突出。互连系统的尺寸变化及先进工艺和TSV技术的采用，导致传统建模方法很难准确提取先进互连系统的寄生电容，从而无法完成对应纳米CMOS电路有效设计与性能优化。基于以上背景，本研究提出"基于3-D EFD方法发展适用于传统及TSV技术的互连系统寄生电容模型研究"课题，在典型互连结构3-D电场分布分析和有效划分基础上，从电场基本原理层面建立覆盖TSV技术的纳米CMOS互连系统的寄生电容模型。 发展的模型应能针对纳米CMOS先进互连技术和3-D堆叠集成电路中的TSV互连技术计算对应的寄生电容，预言几何结构和工艺尺度变化对寄生电容和电路性能的影响规律，从而为对应的纳米电路设计和性能优化奠定仿真基础。

极大规模集成电路制造进入亚45纳米时代，寄生电容问题越来越突出，互连系统的尺寸变化与先进工艺的发展给寄生电容的准确提取带来巨大挑战，可能应用的非传统CMOS器件的复杂结构也造成器件寄生电容参数提取的极大困难，涵盖CMOS器件与互连的统一寄生电容模型难以开发将导致CMOS电路难以得到高效准确的设计与优化。因此，兼顾准确性、效率和灵活性的互连线与非传统CMOS器件的统一寄生电容的模型对于集成电路设计是至关重要的。本研究提出“基于3-D EFD 方法发展适用于传统及TSV 技术的互连系统寄生电容模型研究”项目，争取在 2-3年内在典型结构3-D电场分布分析和有效划分的基础上，建立互连系统、CMOS非传统器件以及典型CMOS电路模块的简约解析电容模型，实现电路设计的优化。该模型应能针对不同的先进互连技术和非传统CMOS器件等求出相应的寄生电容解，并能被嵌入到各种电路模拟系统中。.本项目从基于3-D电场区域划分的角度出发，求解多种基本3-D互连结构的耦合电容的简约解析模型并总结系统的分析方法，帮助人们深化认识到影响各电场区域电容的各种因素，从而应用到CMOS互连结构的寄生电容简约解析模型的建立工作中，建立物理性的基于3-D电场理论和分析方法的CMOS互连系统寄生电容的简约解析模型及开发相应的快速电路仿真软件，从而实现对CMOS电路的设计和性能优化。