SOI功率器件高K介质横向变宽度三维耐压新技术：机理、模型和工艺研究

One of key challenges in semiconductor power device is the proportion between specific on-resistance and breakdown votlage to the 2.5th power.For the scientific issue, this proposal proposes a novel voltage-sustaining technology---Variation of Lateral Width in SOI power devices.The "silicon limit" is broken through and the index reduces drastically from 2.5 to 1.3. In this proposal: 1) A novel voltage-sustaining technology---Variation of Lateral Width is proposed. A high-K dielectric region is inserted into the drift region to form a current conduction path which widens from the source to the drain.As a result, the linearization of doping density and uniformization of the electric field are obtained in three dimensions. Breakdown voltage increases by 100%, on-resistance reduces by 50%, and BFOM value increases by 2-5 times in comparison with conventional RESURF technologies. 2) A novel 3D breakdown voltage modeling method of lateral power devices is proposed. The Poisson equation is resolved using 2D Taylor Expansion and piecewise constant coefficient. The breakdown voltage model is developed to explore the voltage-sustaining mechanism. The model provides a theoretical guideline for the design of the structure parameters due to the simplified analytical expression and clear physical conceptions. 3) A fabrication scheme compatible with CMOS process is proposed and the device is manufactured. Compared to the VLD and VLT technologies, the process complexity reduces sharply due to the fact that only one additional mask is necessary to form the high-K dielectric region. This project riches the voltage-sustaining method of SOI power device theoretically, and thus presents a scientific significance and practical value for power integration technologies.

导通电阻与击穿电压的2.5次方成正比是半导体功率器件面临的主要挑战，在横向功率器件中尤甚。本项目围绕此科学问题，针对SOI横向功率器件，提出一种横向变宽度三维耐压新技术，突破硅耐压极限，使上述2.5次方关系降低到1.3次方关系。主要创新包括：1)在结构上，提出在漂移区插入高K介质区，形成宽度从源到漏逐渐增加的电导区，实现漂移区杂质密度的线性化和电场分布的均匀化。和常规结构相比，击穿电压提高一倍、导通电阻降低一半、BFOM优值提高2-5倍；2)在建模上，提出采用二元泰勒展开和分段常系数化求解三维泊松方程的新方法，建立新器件结构的击穿电压模型，准确揭示工作机理。3)在工艺上，提出兼容标准CMOS工艺的新器件制备方法，在不显著增加工艺复杂度的情况下研制新器件。本研究丰富了功率器件耐压技术，拓展了耐压理论，有望使横向功率器件的性能达到纵向超结的水平，对功率集成技术具有重要科学意义和应用价值。

导通电阻与击穿电压的2.5次方成正比是半导体功率器件面临的主要挑战，在横向功率器件中尤甚。本项目围绕此科学问题，针对SOI横向功率器件，提出一种横向变宽度三维耐压新技术，突破硅耐压极限，使上述2.5次方关系降低到1.3次方关系。在结构设计方面，完成了横向变宽度技术与高K 介质区技术的耐压机理的研究，并对漂移区形状、高K 介质区材料以及几何参数进行优化设计。在理论建模上，基于高k技术的横向功率器件的三维耐压模型，等效耐压模型，阶梯变宽度漂移区器件的三维耐压模型以及线性变宽度漂移区器件的三维电势和电场分布解析模型和击穿电压模型；并运用TCAD 仿真工具对耐压模型进行验证，证明了模型的正确性，准确揭示工作机理。在工艺制备上，提出兼容标准CMOS工艺的新器件制备方法，在不显著增加工艺复杂度的情况下研制新器件。完成三维工艺模拟与工艺参数优化，研究各工艺条件对器件性能的影响，完成工艺设计以及版图设计。基于以上研究，申请人在本领域重要国际期刊和重要国际会议上发表论文39篇，其中SCI收录论文17篇，EI收录论文13篇，申请专利13项，授权专利17项。本研究丰富了功率器件耐压技术，拓展了耐压理论，有望使横向功率器件的性能达到纵向超结的水平，对功率集成技术具有重要科学意义和应用价值。