新型超高压多倍RESURF变掺杂nLDMOS结构及其集成关键技术

Integrated Ultra high voltage (UHV) 500 V - 800 V LDMOS are widely used in AC-DC converter and LED driver. A new UHV multi Reduce SURface Field (RESURF) variational lateral doping n-type LDMOS (MRVLD-nLDMOS) is proposed. Based on quadruple RESURF LDMOS, n-type buried layer (Nbury) is introduced between p-type buried layer (Pbury) and p-type top layer (Ptop) in deep junction n-type well (DNW) drift region. The super junction in the longitudinal direction is shaped to increase the dose of n-type drift region. Meanwhile, the variational lateral doping technology is also introduced with Ptop rings. The shorter n-type drift is achieved. Compared with traditional double RESURF LDMOS and triple RESURF LDMOS, the specific on-resistance (Ron,sp) is reduced by at least 50% and 20%, respectively. In addition, it is easily to be integrated. The Ron and the electric field with breakdown voltage (BVds) analytical models for proposed structure will be researched. The process flow is set up to research the low-cost integrated technology of the device. Ron,sp and BVds related to the structure and process parameters will be studied by simulation software. Finally, the new structure will be experimentally certificated. This research is the first theoretical and realizable study on the multi RESURF technologies in LDMOS. It has an important scientific significance and application value.

可集成超高压LDMOS广泛应用于AC-DC电源管理和LED驱动芯片。本文提出了一种新型超高压多倍（＞3倍）RESURF变掺杂n型LDMOS。基于传统4倍RESURF LDMOS结构，在两个p型RESURF层之间引入n型埋层Nbury，与深n阱漂移区共同形成纵向方向互相耗尽的超结层，获得高的漂移区剂量。同时，引入变掺杂技术，采用分段的表面p型层，形成多峰值表面电场，较之传统结构，拥有更短的漂移区长度。在获得500V-700V耐压前提下，上述两点创新使其比导通电阻较之传统的2倍和3倍RESURF LDMOS，分别至少降低50%和20%，且具有易集成的特点。本研究将推导其电场耐压模型和导通电阻解析模型。借助仿真软件分析器件特性。搭建工艺流程，研究其低成本集成化关键技术。最后，通过流片实验验证。本项目是首次对多倍RESURF LDMOS的理论性和可实现性的研究，具有重要的科学意义和应用价值。

可集成超高压LDMOS广泛应用于AC-DC电源管理和LED驱动芯片。本文提出了一种新型超高压多倍（＞3倍）RESURF变掺杂n型LDMOS，申请了相关专利。基于传统4倍RESURF LDMOS结构，在两个p型RESURF层之间引入n型埋层Nbury，与深n阱漂移区共同形成纵向方向互相耗尽的超结层，获得高的漂移区剂量。同时，引入变掺杂技术，采用分段的表面p型层，形成多峰值表面电场，较之传统结构，拥有更短的漂移区长度。获得的实验结果，对500V/600V/700V LDMOS，击穿电压分别为560V/650V/760V，比导通电阻分别为4.3/6.2/ 7.9 Ω·mm2，比导通电阻较之传统的2倍和3倍RESURF LDMOS，分别至少降低50%和20%。研究了动态导通电阻，首次理论和实验分析了动态导通电阻的问题和解决方法。本研究将该LDMOS集成在700V BCD工艺平台，该平台下获得了高ON-BV的寄生JFET和超低比导通电阻的中压nLDMOS，分别进行了研究并发表论文。本研究推导了其电场耐压模型和导通电阻解析模型。借助仿真软件分析器件特性。搭建工艺流程，研究其低成本集成化关键技术。最后，通过流片实验验证。本项目是首次对多倍RESURF LDMOS的理论性和可实现性的研究，具有重要的科学意义和应用价值。