基于三维集成电路的神经形态芯片互联架构研究

Neuromorphic chip has been gaining popularity and been widely researched due to various benefits, including low power consumption, capability of processing information in an asynchronous, real-time, parallel and distributed way, and the potential of autonomous perception, recognition and learning. Targeting at the problem of high parallelism, high complexity in interconnects, and low scalability in designing large scale neuromorphic chip, this project proposes the research on the interconnect structure of 3D integration based neuromorphic chip. This research combines methodologies and techniques in 3D integrated circuit modeling, 3D integrated circuit design, and 3D network-on-chip design. The goal of this project is to design an 3D interconnect structure for the neuromorphic chip with high aggregated bandwidth and low power consumption. This proposal includes the following three research topics: (1) building the electrical model of through-silicon vias (TSVs) with the consideration of leveraging the large capacitance of TSVs as spiking neurons; (2) leveraging 3D routers in 3D network-on-chip to provide a solution for interconnects in large scale neuromorphic chip; (3) providing the mapping mechanism from one or two typical neural network applications to the designed neuromorphic chip and bringing out the corresponding performance and functional evaluation framework. Through the above three research topics, the expected achievement of this project is the network-on-chip structure design for three-dimensional integration based neuromorphic chips. This achievement can be treated as a foundation for the development of future high performance and low power large scale neuromorphic system.

神经形态芯片由于其低能耗，可以进行异步、实时、并行和分布式数据处理的特性，以及具备自主感知、识别和学习的能力，已经引起了越来越多的关注和研究。本项目针对大规模神经形态芯片的高并发度、互联高复杂度以及低可扩展性的问题，结合三维集成电路建模、三维集成电路设计、以及三维片上网络技术，开展基于三维集成的神经形态芯片架构研究，使得神经形态芯片在达到高带宽的同时保持低功耗。本项目的主要研究内容包括：(1)建立硅穿孔的电特性模型，考虑利用硅穿孔大电容作为脉冲神经元的可能性；(2)利用三维路由构建三维片上网络，为大规模神经形态芯片通信提供方案；(3)针对一到两个典型神经网络应用提出应用到芯片的映射机制并提供相应的性能功能仿真验证方案。通过以上三个方面的研究，本项目的预期成果是提出基于三维集成的神经形态芯片中片上网络架构，为后续的高性能低功耗的大规模神经形态系统奠定良好的基础。

本项目针对神经网络之间互联的高并发性高复杂度以及低扩展性的问题，结合三维硅穿孔的电容建模、三维片上互联架构设计、神经网络应用优化、神经网络加速器设计及映射的技术，按照从底层硬件到体系结构再到应用算法的自下而上的方式，探索了三维集成技术在神经网络芯片上的应用。本项目的主要研究内容和结果包括1）建立三维硅穿孔在不同负载情况下的电容模型，得到其电容数值比神经元电路模型需求小一个数量级，在不经过优化的情况下，无法作为神经元的实现；2）提取FSDD以及NMNIST在LSM神经网络结构下的网络通讯需求，分析二维和三维互联架构情况的网络延迟情况，明确三维互联架构给LSM神经网络带来带宽提升和延迟减小的好处；3）深入优化两种神经网络的典型算法，在降低神经网络复杂度的同时保证其准确率，根据神经网络的特征，用软硬件协同方式设计神经网络加速器，并且给出相应的神经网络计算映射方案，使得最终的神经网络加速器能效比提高。本项目的研究结果表明了三维集成技术在神经网络芯片上应用的技术路线是可行的，为构建高性能、低功耗、高可扩展的大规模神经网络处理系统奠定了理论基础。