Boole过程论中高速ASIC设计自动化新方法研究

The design of high-speed VLSI chips requires novel theories and approaches in design automation. Boolean Process theory is recently proposed to meet this requirement. In this project, on one hand, some theoretical extensions are made based on Boolean process, including concepts such as partial derivative of waveform polynomial, waveform polynomial vector, delay matrix, multi-valued Boolean process, conditionally sensitizational path, waveform distance considering crosstalk, and three-dimentional Boolean process. And based on these concepts, a sensitization theorem for sequential circuits, theorems for transition numbers in circuits and a data structure of generalized list for the representation and manipulation of waveform polynomial are proposed. On the other hand, novel techniques in design automation for high-speed ASIC such as timing, verification, synthesis and test generation are proposed. In exact timing for combinational circuits, a novel exact hierarchical delay analysis method is presented, with good exactness of less-than-3-percent computation error, and it is able to save CPU time of more than 50 percents compared with the original analytical delay model in Boolean process. In timing for sequential circuits, a precise clocking method based on sensitization theorem is presented, with advantages of reducing the traditionally-computed clock cycle more than 60 percents while ensuring of its normal operation. In simulational verification, a waveform simulation approach considering interconnect delay and a parallel waveform simulation method are proposed, with greatly-improvd acceleration ration. In formal verication, a new method that transforms bit-level waveform polynomial to word-level polynomial model is given, providing an efficient way to determine whether two descriptions from different design levels are equivalent, so verification across design levels can be realized. In synthesis, a multi-valued synthesis algorithm based on multi-valued Boolean process and a wired-centered synthesis policy are proposed. In layout design, a nove wiring method with minimal crosstalk is presented. In testing, a test generation approach that could generate the noisiest sensitization waveforms for VDSM design is proposed, accelerating computation of at least two-order quantity compared with traditional SPICE simulation.

完成Boole过程论基本概念、基本运算及其规律、语义学、公理集、演绎系统等系统等内容难芯俊Ｒ谰萃晟坪蟮腂oole过程论完成高速ASIC设计自动化中高级综合、逻辑综合和自动验证三个方面新方法及其形式化描述研究。该理论可以成为相对精确地描述高速度、大集成度、高复杂度IC的数学工具、在此基础上形成一类新的DA方法。