基于延迟特征的三维集成电路硅通孔测试关键技术研究

Through silicon via (TSV) is one key component in three dimensional integrated circuits (3D IC). The yield and reliability of 3D IC is reduced significantly for the unmature manufacturing process and difficulties in test access.. From the point of delay characteristics caused by the defects in TSV, the following contents will be intensively researched in this project: . 1) Aiming at the shortage of existing methods in online monitoring, an online transition delay monitoring structure will be presented based on Schmitt inverter. Wave shaping and hysteresis effect of the Schmitt inverter will be used to translate the transition delay time into rectangular pulse, and then generate a pulse threshold to monitor the transition delay. . 2) Aiming at the problems of limited precision and fault detection range, a time to digital convesion based pre-bond TSV test architecture will be proposed. the pulse at the transmitting end will traverse the cyclic shrinkage cells, and then the shrinkage amount will be captured and digitized into a digital code to compare with an expected value of fault free at the receiver end. Therefore, high precision of picosecond level, wide fault detection range and the capablitiy of fault binning will be realized.. 3) Aiming at the low yield and difficulty in test access of TSV, a test structure based on vernier delay line will be proposed. The difference of gate transmission delay will be used as temporal resolution to achieve higher test accuracy and improve the yield of TSV.. Through this project, it will provide effective key technologies and solutions to improve the reliability and yield of TSV, which will provide remarkable theoretical and practical value to promote the development of 3D IC industry.

硅通孔(TSV)作为三维集成电路(3D IC)的关键部件，其工艺不成熟、测试访问困难，严重影响3D IC可靠性和良率。项目以TSV缺陷引起的延迟特征变化为切入点深入研究以下内容：1)针对现有方法在线监测能力不足问题，提出基于施密特反相器的在线监测结构。利用施密特反相器整形特性和滞后特性将跳变延迟转换为矩形脉冲，然后生成脉宽阈值监测跳变延迟。2)针对测试精度和故障检测范围有限等难题，提出基于时间数字转换的TSV测试结构。发送端脉冲遍历环状缩减单元，在接收端捕获脉冲缩减量并与预期无故障信号的数字码比较，达到皮秒级测试精度和故障检测范围，实现故障分级。3)针对TSV良率不高，测试访问困难问题，提出基于游标延迟线的测试结构。使用门传输延迟的差分作为时序分辨率，实现较高测试精度以提升TSV良率。项目为提升TSV可靠性和良率提供有效的关键技术和解决方案，对促进3D IC产业发展具有重要理论和应用价值。

硅通孔(TSV)作为3D IC中的核心部件，由于新型制造工艺不成熟、测试访问困难，TSV的良率和可靠性易受制造缺陷影响。利用TSV故障引起的延迟特征波动，本项目研究TSV良率和可靠性提升方法中关键基础问题，在TSV测试结构、容错结构设计、3D IC硬件安全防护等方面取得了创新性成果：. 1)研究了TSV测试分辨率、面积开销、故障严重程度与检测范围的定量表征以及多故障并存条件下测试混淆问题的解决方法。设计一种使用施密特触发器作为接收器的TSV测试结构。设计一种基于分布式脉宽缩减的非侵入式2.5D IC互连故障测试结构。提出一种增强式时间数字转换的绑定前TSV双故障测试方案。提出一种基于边沿延时翻转的绑定前TSV测试技术。. 2)研究了面向聚簇故障、时延故障、修复率提升的容错结构设计方法。提出跨细胞式、蜂窝式和时分多路访问式TSV容错结构设计方案。提出一种基于行/列块映射技术的3D存储器内建自修复方案，从而改进冗余资源利用率，降低硬件开销。综合考虑冗余TSV面积和延迟开销，提出一种容忍时延故障的TSV现场修复方案。提出一种基于模拟退火的温度敏感布图规划算法降低3D IC固定框架布局的峰值温度。. 3)研究了3D IC硬件安全防护结构设计方法。提出一种适用于三维集成电路的物理不可克隆函数（PUF）电路结构。利用CMOS器件和TSV的工艺偏差生成安全密钥来抵抗物理攻击。. 4)在IEEE TETC、IEEE TCAD、IEEE TCASII、IEEE Access、JCSC、ELEX、电子学报等国内外期刊发表学术论文12篇，其中SCI检索10篇，EI检索11篇；授权发明专利1件，实用新型专利1件，1件发明专利处于实质审查状态，授权集成电路布图设计专有权2件，获得软件著作权5件；培养出2位硕士，2位硕士生在读。. 本项目研究将有助于提升3D IC产品良率和可靠性、确保产品质量，推动3D IC领域技术创新和集成电路产业发展。