面向舰船信息系统网关的粗粒度可重构处理器关键技术研究

With the increase of massive embedded computing units (ECU) and safety-critical data, the future ship information system requires even greater latency, bandwidth, flexibility and reliability of gateway processor. However, simple combination of existing hardware cannot meet the actual demands of future ship information system. Addressing the issue of future ship information system, this study deeply analyzes the actual demands and algorithmic characteristics, and then proposes a specific coarse-grained reconfigurable processor for the gateway. Specifically, the proposed processor architecture makes full use of the existed parallelism of task level, thread level, and instruction level of gateway data operating process. On the other hand, the typical stream compute-intensive characteristic of gateway data is also used to optimize the proposed processor architecture. Therefore, the proposed processor not only possesses the performance as application specific integrated circuit (ASIC), but also owns the flexibility as general purpose processor. Finally, it is expected that this study can meet the actual demands of gateway and accumulate the technologies for the future ship information system of our country.

未来舰船信息系统海量的嵌入式计算单元和大量的安全关键数据对未来舰船信息系统网关处理器的延迟、带宽、灵活性以及可靠性提出更高要求，基于现有硬件平台的简单堆叠已经无法满足未来舰船信息系统网关的实际需求。本课题在深入分析未来舰船信息系统网关实际需求和算法特征的基础之上，研究面向未来舰船信息系统的网关实现策略，进而提出一种粗粒度可重构专用处理器结构。所提处理器结构充分利用未来舰船信息系统网关数据操作过程中广泛存在的任务级、线程级以及指令级并行和网关数据负载具有的天然流式处理特性，进行体系结构级优化，使得所提处理器兼备接近ASIC的性能和通用处理器的灵活性。本课题研究成果可满足未来舰船信息系统对网关的实际需求，为我国新型舰船信息系统的研究进行技术积累。

未来舰船信息系统海量的嵌入式计算单元和大量的安全关键数据对未来舰船信息系统网关处理器的延迟、带宽、灵活性以及可靠性提出更高要求，基于现有硬件平台的简单堆叠已经无法满足未来舰船信息系统网关的实际需求。利用舰船信息系统网关数据处理过程中广泛存在的任务级、线程级以及指令级并行性以及网关数据的天然流式特性，本课题提出了一种粗粒度可重构专用处理器结构。完成了处理器体系结构设计和关键技术攻关，并基于FPGA建立了一套面向未来舰船信息系统网关的专用处理器原型系统，完成了处理器在原型系统上的部署，并开展了舰船信息系统网关在所提处理器结构上的映射研究。