高精度片上抖动测量关键技术及电路实现研究

Along with the development of semiconductor manufacturing process, the scale and performance of integrated circuit are improving and the accurate jitter measurement plays a crucial role on chip’s performance and yield. However off-chip jitter measurement technology has not been able to meet the measurement requirements in the test cost, time, and accuracy. On-chip jitter measurement technology is of great significance, becoming the research focus of academia and industry. To solve the problem of low accuracy of traditional undersampling and VDL measurement technology and reduce measurement error rate to 1%, this project researches on the effective measurement theory (including measurement node analysis and measurement environment analysis)and high accurate measurement technology. Mutual sampling measurement technology will be adopted to eliminate the test error from the sampling clock jitter and offset. In addition, cycle and median aligned processing technology will be used when measuring period jitter, cycle-to-cycle jitter, long-term jitter. When measuring timing jitter, variable resolution VDL measurement circuit will be designed and digital-controlled self-calibration method will be adopted, which can reduce PVT effects and improve measurement accuracy. Based on these theory and technologies, the proposed circuit will be designed and fabricated on the SMIC 40nm LL process in order to achieve high-accuracy on-chip jitter measurement.

随着半导体制造工艺不断发展，集成电路规模及性能不断提高，精确的抖动测量对芯片的高性能、成品率起着至关重要的作用。然而片外抖动测量在测试成本、测量时间以及测量精度上均已无法满足测量需求，片上抖动测量电路技术具有重要研究意义，已经成为学术界和产业界的热点研究方向。本课题通过抖动测量有效性（抖动测量节点分析、抖动测量环境分析等）的深入研究，针对传统欠采样和游标延时链（VDL）方案存在的精度问题，进行高精度测量关键技术研究，拟将测量误差降低至1%以下。测量周期类抖动时拟采用互采样技术解决采样时钟引入的抖动和偏差问题，并使用中央对齐/周期对齐混合处理技术；测量时间抖动时拟使用多分辨率VDL结构，大幅降低延时链级数，结合数控自校正技术，进一步降低PVT影响，提高测量精度。基于以上理论和技术，本课题将在SMIC 40nm LL工艺点上设计电路并流片测试验证，实现高精度片上抖动测量。

本项目研究内容主要分为四个部分：1、锁相环抖动测量有效性研究，给出各种类型抖动之间的关系、锁相环各节点抖动关系、测量环境对精度的影响等理论分析。2、优化采样信号生成技术，结合互采样和多相位采样，完成电路设计，消除对采样时钟的要求，减少无效采样点，提高测量精度。3、优化采样信息提取技术，开发一种新的平均对齐技术，用数学意义上的对齐处理代替物理意义上的对齐，实现周期类抖动高精度测量。4、优化采样数据处理技术，完成对称舍弃处理电路的设计与优化，在进一步提高测量精度的同时，大幅减少测量电路硬件开销。针对课题提出的基于欠采样技术的高精度片上抖动测量电路，首先在MATLAB平台对其行为级模型进行功能验证，实验结果表明：本课题提出的抖动测量技术测量精度高（测量误差小于1％）且测量范围广（设计最高测试频率达到600MHz）；接着，基于SMIC 40nm LL工艺节点对本课题提出的测量技术进行电路设计与实现，整个电路面积为90.2×101.6μm2，测试结果表明：在1000次采样周期及百毫秒级测试时间内，电路平均测量误差仅为0.85％，小于1％，符合技术指标要求。