高性能二硫化钼晶体管的界面调控与电输运优化

As the scaling trend in traditional Si CMOS starts to face tremendous challenges in terms of further performance enhancement and the increasing requirements of flexibility for portable electronics, potential candidates for future electronics beyond graphene start to emerge and become the research focus in the recent years. atomically thin transition metal dichalcogenides like MoS2 has attracted great attention recently. Unlike graphene , MoS2 has a size bandgap around 1.8 eV and carrier mobility upto 1000 cm^2/Vs . Previously, most device related work focus on the material properties and low field electrical transport from individual devices. However, important technological relevant figures-of-merit, such as current carrying ability, high field transport, and electrical noise, are either still lacking, or far below the silicon counterpart. A thorough understanding and proper evaluation on the performance potential and limit of this material are highly desirable. In this proposal, we plan to study the high-k dielectric growth mechanisms on intrinsic MoS2, its nucleation dynamics as well as the interface states. In order to improve the growth quality of the dielectrics, several pretreatment methods will be introduced including precursor purging and polymer coating. These approaches will help increase the film strength and decrease the interface trap density. As a result, the carrier mobility in a transistor will be improved because of the reduced scattering from interface. Furthermore, introducing high-k dielectrics with high thermal conductivity will improve the carrier velocity at on -state and eliminate the negative differential resistance behavior at high field, thus increasing the reliability and lifetime of the transistor. Another important performance limiting factor is the Schottky barrier formed at the source/drain metal/MoS2 contact. Electro-static control using a double gate structure can tune the barrier height and width, which leads to enhanced carrier transport from thermionic to field-assist tunneling. By effectively improving the main performance limiting factors such as the interface states, carrier mobility, maximum current and sub-threshold slope, MoS2 will have great potential in future electronics.

近年来，基于硅的传统CMOS器件和电路在运行速度及柔性便携等指标上开始落后于人们的需求和工程师们的设计目标。因此，在石墨烯之外的具有禁带宽度的新型二维材料如过渡金属二硫系化物包括二硫化钼MoS2等。这些材料具有1-2 eV左右的禁带宽度及较高迁移率100-1000 cm^2/Vs,很多可以大面积生长的CVD工艺已经逐渐在实验室中得到开发。本项目将主要将通过研究ALD高k介质在本征二维材料二硫化钼上的成膜机理，引入各种官能基团，优化其成膜过程，强化介质可靠性与电学特性，有效降低界面散射中心态密度，提升二硫化钼材料的迁移率，在开态下降低由于界面热导效率低带来的负阻效应，增加晶体管的可靠性以及寿命。通过对源漏肖特基势垒的电学输运机理研究和双栅的静电势调控，改善接触电阻，制备并研究高性能双栅型二硫化钼晶体管。解决二硫化钼晶体管的主要瓶颈和挑战，包括界面特性，电子迁移率，最大饱和电流，开关速度等。

近年来，基于硅的传统CMOS器件和电路在运行速度及柔性便携等指标上开始落后于人们的需求和工程师们的设计目标。因此，在石墨烯之外的新型二维半导体如过渡金属硫系化物包括二硫化钼MoS2等。这些材料具有1-2 eV左右的禁带宽度及较高迁移率100-1000 cm^2/Vs,很多可以大面积生长的CVD工艺已经逐渐在实验室中得到开发。本项目主要研究ALD高k介质可以有效降低界面散射中心态密度，提升二硫化钼材料的迁移率，在开态下降低由于电子自热效应带来的负阻效应，增加晶体管的可靠性以及寿命。通过对源漏肖特基势垒的电学输运机理研究和双栅的静电势调控，改善接触电阻，制备并研究高性能双栅型二硫化钼晶体管。同时，报道了一种通过调控CVD生长期间MoO3前驱体重量在熔融玻璃上来实现具有高迁移率、大尺寸双层MoS2的制备方法。基于CVD双层二硫化钼的短沟道晶体管在300 K时能够提供427 μA/μm的开态电流，在4.3 K时进一步提升为1.52 mA/μm。此外，基于CVD双层二硫化钼的射频晶体管的非本征截止频率为7.2 GHz，最大振荡频率为23 GHz。这些结果对于解决二硫化钼晶体管的主要瓶颈和挑战，包括界面特性，电子迁移率，最大饱和电流，开关速度等有重要参考意义与借鉴作用。