The high breakdown voltage(BV) and low specific on-resistance (Ron)are critical factors for power devices. However, the Ron increases with BV to the 2.5 power,leading to a rapid increase in power comsumption. To address this problem, we have performed the following innovative researchs: 1. A novel lateral power device with junction field plate (JFP) is proposed, and its mechanism to improve the BV and reduce the Ron is investigated. The proposed JFP technology not only breaks through the limit of the increase in the BV, which the metal field plate or resistive field plate can reach,but also reduces the Ron significantly. This technology is generally applicable to the lateral and vertical power devices. The operation mechanism of the proposed device includes: ① The uniform electric field distribution is obtained in JFP with a variable lateral doping profile, and its coupled effect results in a uniform lateral electric field along the drift region of the power deivce. ② The P-region of the JPF depletes the N-drift region of the power device in the vertical direction, and thus reduces the Ron and enhances the vertical electric field strength in the drift region. ③The junction barrier of the JFP overcomes the drawback of the high leakage current existing in the resistive field plate. ④ The N buried layer in the P-substrate not only modulates the bulk electric field distributions between the high-voltage and the low-voltage region,but also extends the the depletion region in the P-substrate, improving the BV. Compared with the conventional LDMOS, the proposed JFP power device improves the BV by 40% and reduces the Ron by 30%. 2.Based on the two dimensional modulation effect of the electric field in the JFP device, a breakdown analytical model of the JFP LDMOS is presented by solving Poisson equation with special boundary conditions. The analytical model provides an universal design guild for the JFP power device. 3. The JFP LDMOS is to be fabricated experimentally. This project has high innovative significance and practical value.
功率器件的关键是实现高压BV和低比导通电阻Ron,但Ron随BV的2.5次方增加。为此,进行以下创新研究:1.提出结型场板横向功率器件新结构,揭示其提高BV和降低Ron的机理。结型场板突破金属场板和电阻场板提升耐压的极限,且显著降低Ron。该技术普适于横向和纵向功率器件。器件机理:① 横向变掺杂的结型场板内电场均匀分布,其耦合作用使器件漂移区电场横向趋于均匀,提高BV;②结型场板(的P区)对N漂移区纵向耗尽,降低Ron,并增强纵向电场;③结型场板的结势垒克服电阻场板泄漏电流高的缺陷。④P衬底中的N埋层调制高、低压两端的体电场,扩展衬底耗尽区,改善BV。相比常规LDMOS,BV提高40%且Ron降低30%。2.基于结型场板的二维电场调制效应,求解特殊边界条件的泊松方程,建立结型场板功率器件的耐压解析模型,为结型场板器件提供普适的设计指导。3.研制结型场板LDMOS。项目具有创新性和实用价值。
兼具高击穿电压 (Breakdown Voltage, BV) 和低比导通电阻(Specific On-Resistance,Ron,sp)是功率MOSFET器件研究的热点科学问题,然而,存在困扰业界的Ron,sp∝BV 2.5的“硅极限”关系。为此,本项目从器件新结构,模型以及工艺实现等几个方面展开研究,成果突破了“硅极限”。本项目已经实现了预期目标,完全达到技术指标。取得的创新成果如下:.(1) 提出系列结型场板横向功率器件新结构,揭示其提高BV和降低Ron,sp的机理。新器件表面引入由PN结组成的结型场板结构,该结型场板结构不仅提升耐压,且显著降低Ron,sp。机理如下:① 横向变掺杂的结型场板内电场均匀分布,其耦合作用使器件漂移区电场横向趋于均匀,提高BV;② 结型场板中的P区对N漂移区(针对N沟道LDMOS)纵向辅助耗尽,提高漂移区掺杂浓度以降低Ron,sp;③ 结型场板的结势垒克服电阻场板泄漏电流高的缺陷。.(2) 建立了结型场板功率器件的耐压解析模型,为结型场板功率器件提供普适的设计指导,也为功率MOS器件设计提供了新的设计思路。.(3) 研制了具有结型场板的LDMOS样品,项目具有创新性和实用价值。研制的P沟道具有结型场板pLDMOS (JFP-PFL pLDMOS)样品耐压达到527V,比导通电阻值为323.7mΩ·cm2,比常规pLDMOS器件的耐压提高了41.7%且比导通电阻降低了57.8%。研制的N沟道具有结型场板的LDMOS样品耐压达到580V,而相同漂移区浓度下的常规LDMOS器件耐压仅为80V。实验结果验证了新器件的工作机理。.(4) 以该项目研究成果为主要支撑内容获得教育部自然科学二等奖和四川省科学技术进步奖一等奖;发表论文28篇(SCI检索共20篇,全部EI检索),含领域顶级期刊IEEE Electron Device Lett.(EDL)和IEEE Trans. on Electron Device(TED)论文10篇,在功率半导体领域顶级会议ISPSD发表6篇;获授权美国专利1项、授权中国发明专利9项,已受理中国发明专利申请12项。..全部达到了预期目标。
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数据更新时间:2023-05-31
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