基于光子域调制的硅基光电高速收发芯片关键技术的研究

Optical interconnects feature the high bandwidth and low loss, while silicon photonics, which are fabricated in the circuit-compatible process, help to realize the higher integrity, higher power-efficiency and lower cost. With the development of CMOS and SiP process, small-scale electrical-circuits and optical-devices are now approaching to the maturity. However, to realize a larger-scale transceiver system is still challenging. This project focuses on key techniques in silicon optical-electronic (O-E) high-speed transceivers, including: .(1) setting up the O-E mixed-signal device model, and proposing a new transboundary analyzing method, .(2) exploring the system architecture based on high-order optical-domain modulations, .(3) studying the driving, receiving and signal processing circuits under the Pulse Amplitude Modulation (PAM), as well as realizing the transceiver IC in CMOS process, .(4) researching the wavelength self-tuning and signal-decision alto-threshold algorithm, by building a O-E closed-loop control system. .This project is committed to contribute to key devices, circuits, systems and algorithms in O-E transceivers, which would build up a solid foundation for the next generation high-speed, low-power and high-density optical interconnects.

光互连具备高带宽、低损耗的优势，而硅基光电子在集成电路兼容的工艺下制备光器件，实现高集成度、高能效和低成本。随着CMOS和硅光子工艺的发展，硅光器件已近成熟，而光电集成收发机系统的实现仍充满挑战。本课题围绕硅基光电高速收发机关键共性技术，进行如下方面研究：.（1）建立光电混合信号的器件模型，提出跨电子/光子域的联合分析方法；.（2）探索光子域高阶调制下集成收发机的新型系统架构；.（3）研究脉冲幅度调制（PAM）下驱动、接收和信号恢复等电路技术，并采用CMOS工艺实现收发机系统芯片;.（4）研究高阶调制下系统对波长调谐和数据判决的自适应算法，并建立光电闭环电路实现。.总之，本课题致力于解决光电集成收发机从器件建模、电路、系统到算法的一整套设计问题，为实现下一代高速、低功耗、高密度光互联奠定研究基础。

光互连具备高带宽、低损耗的优势，而CMOS兼容工艺下硅光器件和高速电路的融合，可实现集成度、能效的显著提升和成本有效下降。本项目创新了硅光器件，协同设计数模混合电路，突破了器件建模、光电联合仿真、定制化均衡、光电闭环自适应调控等关键技术，最终取得的主要成果包括：.1）提出光子域多幅调制和数字分布式驱动电路技术，先后实现了两段式和多段式的50Gb/s PAM4调制光电集成发射机芯片，仅2VPP驱动电压下（降低33%），实现9.8dB消光比（提升≥3dB）、1.39pJ/bit/dB综合能耗效率（提升36%）；.2）提出了分布式推挽结构驱动电路，先后实现单片8×56Gb/s的硅光驱动芯片和8×56Gb/s的激光器驱动芯片，带宽和集成度达到发表当年国际先进水平；.3）提出“欠带宽放大的后级均衡”技术，实现PAM4调制下64Gb/s和100Gb/s通道速率的硅基光电集成接收机，TIA电路等效输入噪声达到3.2uA；.4）提出一种波特率采样的PAM4数据与时钟恢复方法，实现50Gb/s速率的CDR电路并集成到驱动芯片，实现时钟频率和分布功耗的减半，PAM4解调误码率仅10-12（降低3个数量级）。.本项目研究意义在于，通过对硅光器件结构和电路架构的协同创新，有效提升了芯片的集成度、总带宽和能耗效率，探索了先进工艺CMOS电路与硅光芯片融合集成的可行的技术路线，为下一步片间、芯上的硅基光互连研究奠定了坚实的技术基础。