In the past ten years, as an emerging theory and technology, chip-level physical unclonable function (PUF) gets significant development and successively applies in integrated circuit information protection area. Compared to other anti-invasive and anti-reverse engineering IC design techniques, CMOS chip-level PUF, which consists of on-chip fingerprint and on-chip challenge-response algorithm, performs significant advantages such as cost, area, power consumption and security. However, the on-chip fingerprint design and fabrication techniques are still immature. Many topics such as how to realize temperature immune, resist to supply noise and power-on logic error are not completely solved. In addition, the challenge-response algorithm based on on-chip constant-stable fingerprint just started. Technical efforts on the related modeling, digital implementation, post-process analysis and optimization are urgently expected. Therefore, we propose this project of "Research on chip-level physical unclonable function based on CMOS antenna effect on-chip constant-stable fingerprint". Hopefully we can realize the CMOS chip-level PUF by solving the above-mentioned problems, and provide a set of economic and effective solutions for the information security protection of physical layer.
芯片级物理不可复制功能作为一种新兴的理论和技术,最近十年在集成电路安全保护领域取得了长足的发展并成功地得到了应用。与已有的其他反侵入式和反逆向工程的芯片防护技术相比,以片上指纹和片上挑战响应算法为核心模块的CMOS芯片级物理不可复制功能在成本、面积、功耗和安全性等诸多方面都表现出了极大的优势。然而,关于高稳定性片上指纹的设计制备研究尚不成熟,诸如实现免疫温度变化,抵抗电源噪声的影响,上电复位逻辑错误等目标的大量课题都仍未彻底解决。此外,基于恒稳定片上指纹的挑战响应算法的研究尚属起步,相关建模、数字化实现、集成后续分析优化等方面的技术亟待开发。鉴于此,我们提出"基于CMOS天线效应片上恒稳定指纹的物理不可复制功能研究"项目,希望在综合解决上述问题基础上实现新一代的CMOS芯片级物理不可复制功能系统,为物理层信息安全保护提供经济高效的解决方案。
本项目属于基于先进工艺的高可靠性数模混合集成电路设计领域。项目根据负责人长期在CMOS 模拟和数字混合集成电路领域的研究积累,以及在可信集成电路设计领域的前期主要成果为基础,以片上恒稳定指纹和与之匹配的挑战响应算法的研制为主线,以综合提高CMOS 芯片物理不可复制功能的稳定性,低功耗和低成本为目标,以片上指纹设计及优化为研究的切入点,以片上指纹设计-结构优化-挑战响应算法-芯片验证为研究内容。系统研究芯片级物理不可复制功能的创新理论,探索基于天线效应片上恒稳定指纹的优化,提出一种与之配套的挑战响应算法,为提高我国芯片级信息安全保护提供重要的理论和技术支撑。圆满完成预期的研究目标。依托本基金支持,以第一作者或通讯作者发表IEEE Trans. SCI期刊论文7篇,获权发明专利5项,研制芯片并成功完成流片5款。
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数据更新时间:2023-05-31
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