微纳米尺度无铅焊点及金属聚合物层间破坏机理研究

With continuing reduction in size and the transition to high performance electronic devices, microelectronic packaging has much denser solder joints and higher working current density. Solder joint integrity is recognized as a key issue in the reliability of flip chip and ball grid arrays in integrated circuit packages. Significant reductions in the solder-joint interconnect size results in both the increased volume fraction of brittle intermetallics in the joint and joule heating due to high current density. Previously, the prevalent failure mode in a solder joint was the ductile thermo-mechanical fracture of solder material due to repeated thermal cycling. Most of the traditional researches focus on the fatigue and creep damage of solder joints due to thermal stress which caused by the mismatch in thermal expansion coefficient between silicon die, substrate components and printed circuit board. With the widely application of lead-free solders and the size of solder joints reducing to micro-nano scale in the latest electronic devices, the effect of intermetallic compound (IMC) to the lifetime and performance of solder joints has increased sharply. Leading to a new joints failure mode represented by the layer quasi-brittle failure in solder bulk/IMC. This project combines experiments, theoretical analysis and numerical simulation to study failure mechanism of micro-nano scale solder bulk/IMC interface. The lead-free solder material properties under different temperature and current intensities will be tested. Failure mechanism of solder and BGA packaging under coupled thermal-electricity-mechanical boundary conditions will be investigated. The emphasis of this project is to study the bulk solder/IMC interfacial failure in solder interconnect caused by fatigue thermal stress, Joule heat and current crowding effect. The electric thermo-electrical properties of lead-free solder materials under different working conditions will be tested to provide accurate input parameters to the theoretical and computational model. The damage and failure mechanism of microelectronics packaging connection structure will be studied based on the proposed workflow.

随着电子设备向小型化及高性能化发展，微电子封装结构中高密集度焊点在不同工作条件下的破坏机理与损伤检测是目前国内需求迫切、应用前景广阔的研究方向。传统研究主要针对由于芯片和基板元器件与印制电路板材料热膨胀系数的差异在焊点内产生热应力造成焊点的疲劳、蠕变损伤。近年来，由于无铅钎料的广泛采用以及新型电子设备中的焊点尺寸缩小至微纳米尺度，金属聚合物对焊点工作性能和寿命也带来越来越大的影响，并引起了以焊球/金属聚合物层间准脆性破坏为代表的新的焊点破坏模式。本项目将通过试验、结合理论分析和数值仿真研究无铅焊点在不同温度和电流强度下的材料特性以及试件在热-电-力复合载荷作用下的破坏机理。重点研究疲劳热应力、焦耳热以及电流密集效应等因素引起焊球/金属聚合物层间破坏对焊点性能的影响，从而了解微尺度无铅焊点在不同工作条件下的电热力学性能、损伤及破坏机理及其对微电子封装连接结构工作性能的影响。

微电子封装结构是电子器件的核心部件之一，不只起到支撑芯片的作用，而且负责芯片与电路的电流信息传送，在芯片工作过程中产生的大量的热，也需要封装结构提供导热通路耗散掉。封装结构的安全性对电子设备的性能及可靠性有至关重要的作用。电子器件不断向小型化，对电子组装技术提出了更高的要求，新的高密度组装技术不断涌现。在复合荷载下的钎料热电力学性能和焊点可靠性已成为国际关注的技术问题，同时也是目前限制微电子封装技术发展的瓶颈之一。由于封装连接结构在工作条件下受到热、电、力等多场载荷，因此连接结构的失效问题是多物理场耦合加载导致的，这也是目前研究的难点之一。本项目从材料宏观力学性能、高电流密度下微孔洞演化及焊点疲劳寿命预测三个方面对微电子封装结构中高密集度焊点在不同工作条件下的破坏机理进行了研究。材料宏观力学性能研究主要分为两个部分。一是建立焊料在多场条件下的变形描述方程，结合现有粘塑性本构模型，开发出了适用于焊料的统一蠕变塑性本构模型，从连续介质损伤力学出发，开发了焊料在多场加载条件下的疲劳损伤演化理论，通过将开发的本构和损伤模型耦合，实现焊点结构疲劳的全过程模拟。二是针对无铅焊点\金属间聚合物（IMC）层间断裂进行实验研究，分析IMC生长机理及对焊点结构力学性能的影响。高电流密度下微孔洞演化研究主要针对电迁移导致的孔洞萌生和扩展，基于质量守恒等基本原理，开发了电流密度与孔洞萌生、形貌演化等的力学表征模型。焊点疲劳破坏是封装结构失效的主要形式之一。本项目从能量的观点出发，基于申请人开发的相变理论，利用极值定理，建立焊料疲劳裂纹萌生预测模型。通过上述研究，初步建立了无铅焊点安全性评估体系，并与相关国防科研单位展开合作研究，积极将成果应用到工业实践中。