三维堆叠内存计算系统的可扩展性研究

As the manufacturing technology, architecture and application continue to advance at a dramatic rate, the long-distance data movement between the computation logic and memory has become a severe problem. Currently, the most effective approach to alleviate the data movement problem is the 3D-stacked in-memory computing system. However, due to the constraints from packaging, area and thermal dissipation, it is very challenging to scale the in-memory computing system for efficiently processing large-scale problems. To build a scalable in-memory computing system, it is required to address three main challenges, i.e., hardware communication, software programming, and architecture evaluation and optimization..To address the above three challenges, our project studies a series of key techniques of the scalability of in-memory computing systems. Concretely, our team plans to investigate: (1) the highly-efficient interconnect and data communication mechanism between the computation logic and memory, (2) a programming model compatible with existing mature heterogeneous and parallel programming interfaces, and (3) scalable architectural modeling and optimization approaches for the high-dimensional design space of in-memory computing systems. The research objective of our project is to develop a series of key techniques for scaling out the 3D-stacked in-memory computing systems, so as to facilitate the design and development of domestic intelligent and high performance processors.

随着制造工艺、体系结构和应用程序的快速发展，计算单元与存储逻辑之间的长距离数据搬移问题也日益严重。目前最为有效的缓解数据搬移问题的解决方案是基于三维堆叠的内存计算系统。但由于封装、面积和散热等问题的限制，该系统面临的主要挑战是可扩展性不够，导致难以高效地处理大规模问题。为了对该内存计算系统进行大规模扩展，需要解决来自硬件通讯、软件编程和结构评估与优化等三方面的挑战。.本项目面向这三大挑战，研究三维堆叠内存计算系统可扩展性的一系列关键技术。具体而言，项目组拟重点研究：（1）计算和存储间可扩展互连和数据通讯机制；（2）兼容现有异构并行编程接口的可扩展编程模型及其运行时系统；（3）面向内存计算系统高维空间的可扩展结构建模与优化方法。项目研究目标是形成对三维堆叠内存计算系统进行大规模横向扩展的一系列关键技术，为国产智能处理器芯片和高性能服务器芯片的研发提供有效参考。

随着制造工艺、体系结构和应用程序的快速发展，计算单元与存储逻辑之间的长距离数据搬移问题也日益严重。目前最为有效的缓解数据搬移问题的解决方案是基于三维堆叠的内存计算系统。但由于封装、面积和散热等问题的限制，该系统面临的主要挑战是可扩展性不够，导致难以高效地处理大规模问题。为了对该内存计算系统进行大规模扩展，需要解决来自硬件通讯、软件编程和结构评估与优化等三方面的挑战。. 面向这三大挑战，本项目研究三维堆叠内存计算系统可扩展性的一系列关键技术，包括：（1）计算和存储间可扩展互连和数据通讯机制；（2）兼容现有异构并行编程接口的可扩展编程模型及其运行时系统；（3）面向内存计算系统高维空间的可扩展结构建模与优化方法。. 在计算存储互联及数据通信机制方面，提出了计算和存储间数据划分机制；在可扩展编程模型和运行时系统方面，构建了兼容异构并行编程接口的编程模型及其运行时系统，并在智能处理器上得到应用；在可扩展结构建模与优化方法方面，提出了软硬件协同结构建模与优化，并应用于稀疏神经网络处理器的性能建模与优化中。. 项目共发表论文12篇，其中CCF-A类论文7篇。已形成的关键技术未来有望为国产智能处理器芯片和高性能服务器芯片的研发提供参考。