With the development of optical interconnection towards a shorter distance between chips or even within chips, there will be more frequent optical/electrical or electrical/optical conversion between optical transmission and electrical processing, which will bring additional energy consumption and rate bottleneck. Therefore, it is necessary to directly use optical computing to realize information processing. All-optical logic operation is one of the difficulties in optical computing. Based on the reported integration schemes of basic logic functions such as AND gate and NOT gate, and further combined with the advantage of the parallel processing of optical signal, multiple logic function outputs can be obtained in a single logic device, then all-optical programmable logic array with flexible operation and expanded computing capacity can be realized. Based on the previous research, the project develops 40Gb/s expanded programmable logic array chip to realize arbitrary two-input or three-input combinational logic function, by combining the multi-channel minterms generation in the silicon waveguide using the four-wave mixing effect, with flexible precoding process of the delayed interferometer. The expanded programmable logic array contains three sets of three-input programmable logic array and twelve sets of two-input programmable logic array. The chip has flexible operation and complex functions. The chip can achieve the functions of complex logic devices simultaneously, include full adder,full subtracter, one to two line data distributor, two to one line data selector and digital comparator.
随着光互连向着芯片间甚至芯片内的更短距离发展,光传输和电处理之间将会有更频繁的光/电或者电/光转换,并带来额外的能耗与速率瓶颈,因此有必要直接采用光运算来实现信息处理。全光逻辑运算是光运算中的难点之一,在目前报道的与门、非门等基本的逻辑功能集成方案的基础上,进一步结合光载波的并行处理优势,基于单个逻辑器件实现多个逻辑功能输出,从而实现运算灵活、计算容量扩展型的全光可编程逻辑阵列。本项目在前期研究基础之上,提出基于硅波导中的四波混频效应产生多信道最小项,并结合延时干涉仪预编码的灵活性,开发40Gb/s计算容量扩展型可编程逻辑阵列芯片,该扩展型可编程逻辑阵列可实现3套三输入可编程逻辑阵列和12套两输入可编程逻辑阵列。该芯片运算灵活、功能全面,可以实现两、三输入任意组合逻辑功能,并同时实现全加器、全减器、1线到2线数据分配器、2线到1线数据选择器、数值比较器等复杂逻辑器件功能。
可编程逻辑阵列芯片在数字光计算领域有着重要的价值。利用光的并行性优势构建的扩展型可编程逻辑阵列,可以进一步扩大逻辑运算系统的计算容量。本项目在深入研究基于延时干涉仪和非线性硅基波导的扩展型可编程逻辑阵列理论模型基础上,分析了非线性硅基波导中四波混频效应增强问题,实现了非线性器件的优化设计和工艺制作;利用非线性增强的硅波导结合延时干涉仪预编码实现扩展型可编程逻辑阵列的功能验证,实现两输入、三输入任意组合逻辑功能,并进一步实现全加器、全减器等复杂逻辑功能。. 本项目研制了反向偏置PIN结的硅波导来增强四波混频效应,使得转换后的光信号输出功率提高10dB以上,并实验证明了40Gb/s的全光可重构两输入最小项七个波长通道组播;还制备了硅基-聚合物狭缝波导增强四波混频效应,在3mm长度的硅基狭缝-聚合物波导上实现了-27.5dB的FWM转换效率;基于非线性增强波导研制了50Gb/s可编程逻辑阵列芯片,实现了两输入任意组合逻辑运算功能;基于扩展型三输入可编程逻辑阵列架构,实验验证了一系列组合逻辑功能,包括两、三输入任意组合逻辑功能、全加器、全减器和二比特乘法器功能。相关研究成果发表了系列论文,从芯片研制到系统应用进行详细报道。
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数据更新时间:2023-05-31
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