暗硅时代新型热可靠众核系统的性能与能耗优化关键技术研究

With the maturity of nanotechnology and chip integration techniques, the development of multi-processor systems-on-chip has entered the era of heterogeneous many-core systems. By integrating tens or even hundreds of cores with different computation capability and energy efficiency, a single chip can provide higher scalability and performance per watt for the increasingly complex applications. However, limited by the heat dissipation, packaging and power budgeting techniques, a fraction of the cores has to be turned off or set in the low-power states at runtime in order to guarantee the system reliability, i.e., the dark silicon phenomenon. In this project, we propose novel hardware/software codesign methodology and techniques to address the brand-new challenges brought by dark silicon on the optimization of thermal reliability, performance and power efficiency of heterogeneous many-core systems. On the hardware side, we propose three different architecture designs for the on-chip interconnection network to balance the tradeoff between the thermal reliability and communication efficiency. On the software side, we propose matched task mapping algorithms, respectively, to fully utilize the new hardware designs. By combining the proposed cluster-based management strategy for the heterogeneous many cores, the application performance and system energy consumption are optimized. The hardware-software combined approach realizes the collaborative optimization and maximization of the thermal reliability, performance and energy efficiency of the system. The output of this research project will provide strong technological support for the design of next-generation high-performance low-power heterogeneous many-core systems-on-chip.

随着纳米工艺和芯片集成技术愈趋成熟，片上多核系统的发展进入异构众核时代。单个芯片上集成十余个乃至数百个具有不同计算能力和能耗表现的计算核心，将为日益复杂的应用场景提供强大的可扩展能力及更高的性能能耗比。然而，受到芯片散热、封装和供电能力的制约，部分计算核心必须动态地关闭或运行在低功耗状态下以保证系统可靠性，即暗硅现象。为解决暗硅给异构众核系统的热可靠性、性能与能耗间的协同优化带来的全新挑战，本课题创新地提出一套软硬件协同设计方法和技术：硬件上提出三种不同的片上互连网络的体系结构设计，用于均衡芯片的热可靠性与通信性能间的矛盾；软件上分别提出相匹配的任务映射算法，以充分利用新的硬件设计，结合新提出的集群式异构众核管理机制，实现应用执行性能与系统能耗的优化；软硬件结合实现了系统热可靠性、性能与能耗三者间的协同优化与最大化。本课题的研究成果将为高性能低功耗异构众核片上系统的设计提供有力的技术支撑。

为解决暗硅给异构众核系统的热可靠性、性能与能耗间的协同优化带来的全新挑战，本课题创新地提出一套软硬件协同设计方法和技术：硬件上提出了新的片上互连网络的体系架构，用于均衡芯片的热可靠性与通信性能间的矛盾；软件上分别提出相匹配的任务映射算法，以充分利用新的硬件设计，结合新提出的集群式异构众核管理机制，实现应用执行性能与系统能耗的优化。项目所提出的基于折环式的片上网络互联架构（Folded Torus Like NoC，简称FoToNoC），以及基于四核集群的异构片上网络众核系统架构（Quad-core NoC，简称QcNoC），相比2-D Mesh 网状结构和ARM big.LITTLE 的片上网络处理器架构而言，能够分别获得平均42.21%，31.75%和48.17%，36.56%的提升。项目所提出的针对子任务特性的DVFS调节技术，能够更加精确地为每一个子任务找到最节能的计算状态，有利于系统整体的能耗优化。相比传统的2-D Mesh 网状结构和NoC-Spring 方法而言，系统的能耗能够平均降低28.4%、31.7%和33.5%，且整个芯片的峰值温度始终处于安全温度值81.8℃之下。基于这些研究，项目超额完成了任务书的各项指标，在国际和国内重要学术期刊/会议上发表具有影响力的学术论文18篇，培养了11名优秀的研究生，积极参与及组织了8次重要学术交流活动。 本课题的研究成果将为高性能低功耗异构众核片上系统的设计提供一定的技术支撑。