多微通道内存控制器关键技术的研究

Multiple threads run simultaneously in chip multiprocessors (CMP) which are integrated in a single chip. A CMP system consists of multiple independent processing cores that can access the memory system concurrently. The organization of CMP systems has benefits in terms of power-efficiency, scalability, and system throughput compared to single-core systems. However, the resource management problem posed by the sharing of last level cache, interconnection and DRAM system is significant in designing CMP platforms. The demands of the working-set size from increasingly complex applications has led to the dramatically increase of memory bandwidth and capacity. Therefore memory system contributes significantly to the power consumption of the overall system, and the memory power consumption has approached to that of processors. This study is focused on improving bandwidth utilization, reducing average latency and achieving high power efficiency of DRAM systems. Nowadays, with the increasing demand for high memory bandwidth from multi-core processors, the data bus frequency of a DRAM system has increased beyond 400MHz besides the use of double data transfer. For example, a DDR3-1600 DRAM system runs at 800MHz and can transfer a 64-byte cache block in 5ns. A typical memory device may provide 4-bit (X4), 8-bit (X8) or 16-bit (X16) data output. A DRAM rank groups several DRAM devices together to serve requests from the memory controller. A JEDEC standardized DRAM system is organized by ranks that operate on a 64-bit data bus. The use of 64-bit rank is good for reducing the data transfer time and thus memory idle latency, but it is a limit for DRAM system to allow meaningful trade-offs between performance and power According to the memory system performance model that we proposed previously, we analyze the key features that affect the performance of the memory system. We propose a new dynamic channel allocate mechanism for multiple micro-channel memory access controller. Different data streams corresponding to different DRAM commands can flow from or to DRAM devices concurrently. The memory queuing latency can be reduced, and the proposed memory access controller achieves the best performance/power efficiency. We introduce a novel memory access scheduling algorithm that is good for reducing the memory request queuing time and improving data bus parallelism, which obtains high DRAM data bus utilization.In order to effectively manage the bandwidth resource of multiple micro-channel memory controller, we put forward a set of virtualization solution for multiple micro-channel memory controllers. As a shared platform between the physical memory access controllers and logical memory controllers, the memory controller virtualization platform needs to manage the physical multiple micro-channel memory access controller efficiently, which can enhance performance of the CMP by improving the utilization of memory bandwidth.

多核处理器的发展对内存系统的延迟、带宽和功耗等方面提出了更高的要求。针对这种情况，本课题申请人提出过一种多微通道内存控制器设计方法。该内存控制器可以在提高内存系统带宽利用率的同时，缩短访存请求延迟，并具有较高的性能功耗有效性。在后续的研究中发现，现有的多微通道内存控制器不能实时侦测应用程序访存特性的变化趋势，从而动态的在应用程序间分配微通道，在实际应用中具有一定的局限性。本课题旨在三个方面对多微通道内存控制器设计进行优化：(1)引入动态通道分配机制。该机制可以更加灵活的在进程间分配微通道，具有更高的实用价值。(2)提出一种适用于多微通道内存控制器的协同访存调度算法。该算法不但可以使不同的微通道对进程优先级有相同的认识，还有低通信量和高扩展性等特征。(3)提出一套多微通道内存控制器虚拟化方案。该方案可以对多微通道内存控制器的通道资源进行有效管理，具有多实例、隔离性和高性能等特征。