超薄高K栅介质的声子能量耦合物理效应研究

According to Moore's law,microelectronic industry has to scale down the transistors on integrated circuit. The industry is interested in the HfO2/IL gate stack with an equivalent oxide thickness (EOT) of 0.6-1.0 nm, where the IL layer is 0.4-0.7nm.The proposed lateral heating process (LHP) that can induce Phonon Energy Couping Effect (PECE)and structure changes in the silicon near the oxide/Si interface is used to reduce the tunneling current of the HfO2/IL stacks and enhance the reliability of the IL layer as well.In this proposal, we will pursue the following project objectives:(1) Research on the physcial mechanism of PECE and structure changes in oxide/Siinterface.(2) Growth of HfO2 on a chemical oxide interfacial layer (IL) with an EOT of0.6-1.0 nm using atomic layer deposition and the reliability of IL is improved.(3) The leakage current of ultra-thin HfO2/IL gate stacks and power consuming of MOS devices are reduced dramatically.

根据摩尔定律,微电子工业界必须不断缩小集成电路上晶体管尺寸,从而要求高k栅介质及界面(IL)的等效氧化物厚度(EOT)减小至0.6-1nm（其中界面层EOT约为0.4-0.7nm）。本项目提出横向加热(LHP)工艺方法不仅可以在氧化层内或者氧化层/硅界面附近引起声子能量耦合效应（PECE）,减小HfO2/IL栅叠层的隧道效应漏电流，而且可以提高栅叠层的可靠性。本项目最终实现如下研究目标：(1)研究声子能量耦合物理效应在氧化物/界面层及硅衬底中产生的物理机理；(2)采用原子层沉积（ALD）工艺方法，制备EOT为0.6-1nm的HfO2/IL栅叠层并提高栅叠层的可靠性；(3)大幅降低基于超薄HfO2/IL栅叠层的MOS器件的漏电流和功耗。

本项目研究针对摩尔定律极限问题,解决微电子集成电路中随着晶体管不断缩小，必须不断缩短晶体管沟道长度，从而要求不断减薄栅介质层厚度带来的漏电流不断增大的问题。实验证明高k栅介质及界面(IL)的等效氧化物厚度(EOT)减小至0.6-1nm则达到了物理极限。在本项目中，我们采用横向加热(LHP)工艺方法不仅可以在氧化层内或者氧化层/硅界面附近引起声子能量耦合效应（PECE）,大幅减小HfO2/IL栅叠层的隧道效应漏电流，证明可能进一步减小物理厚度，缩小晶体管尺寸，同时提高了栅叠层的可靠性，降低集成电路功耗。本项目最终实现了如下研究目标：(1)研究声子能量耦合物理效应在氧化物/界面层及硅衬底中产生的物理机理；(2)采用原子层沉积（ALD）工艺方法，制备EOT为0.6-1nm的HfO2/IL栅叠层并提高栅叠层的可靠性；(3)大幅降低基于超薄HfO2/IL栅叠层的MOS器件的漏电流和功耗。