基于延时-相位域的全数字锁相环设计研究

As the shrinking of supply voltage and the device size for the nano-scale CMOS process, a high-performance and low-power phase-locked loop design becomes a great challenge. However, the reduction of the device delay brings an opportunity for the mixed-signal design in the time delay/phase domain. In this project, we will focus on the all-digital phase-locked loop design, to get a high FOM value. A high-order noise shaping technique in the phase domain is proposed to reduce the TDC quantization noise and increase its time resolution, the related theory and circuit implementations will be studied. A 3rd order ΣΔ modulation TDC based on the switched ring oscillator will be proposed, and the nonlinearity of the analog delay unit of the ring oscillator will be compensated. Meanwhile, a low noise Class-A LC-DCO, a low power TSPC divider, the dynamic supply voltage regulation techniques and nonlinearity calibration method will be proposed, and finally to achieve a low power, low phase noise and robust ADPLL circuit, meeting the specifications in the phase noise, frequency accuracy, spurious level and other aspects of the performance requirements.

电源电压的降低和器件尺寸的缩小对纳米尺度下的高性能、低功耗锁相环设计带来了巨大的挑战，但器件延时的降低使得基于延时/相位域的数模混合设计成为新的契机。本项目将围绕高品质因子的全数字锁相环设计，提出利用相位域的高阶∑△调制技术降低TDC的低频量化噪声和提高时间分辨率，本项目将对这一相位域处理技术进行理论和电路实现研究，提出一种基于切换型环形振荡器的三阶ΣΔ调制方式的TDC结构，实现TDC量化噪声调制和整形，同时将提出补偿技术降低其中环形振荡器模拟延迟单元的非线性。项目还将提出低相位噪声的Class A型LC-DCO电路、低功耗TSPC分频器电路，并结合电源电压调节技术和非线性校准技术，从而最终实现纳米CMOS工艺下具有低功耗、低相位噪声和工艺鲁棒性的全数字锁相环结构，满足本振信号在相位噪声、频率精度、杂散抑制等方面的性能要求。

随着CMOS工艺尺寸的持续缩小，晶体管的本征延时减小，使得时域信号处理电路能够实现更高的精度和分辨率，但纳米CMOS工艺下低电源电压以及工艺PVT变化也给电路设计造成了较大困扰。本项目从时域角度对纳米CMOS工艺下的全数字锁相环设计开展研究，研究成果如下：1）设计了一种高线性度的时间/相位域信号相关运算单元，包括加法、减法和积分（累加）电路，提出了一种交替输入的时间积分器，逐周期消除晶体管泄漏电流引起的时间积分误差；2）提出了一种谐振回路的电感分段调谐方式提高数控振荡器的频率分辨率，提高了输出振荡幅度，降低了量化噪声和晶体管闪烁噪声对相位噪声的贡献；3）提出了一种电容耦合的噪声循环压控振荡器，降低了晶体管噪声注入LC谐振回路的噪声，具有宽频率调谐范围、低相位噪声的优势；4）设计了三阶∆∑时间数字转换器，采用LMS算法针对PVT变化和工艺失配造成的非线性进行校准；最终采用TSMC 28nm CMOS工艺对全数字锁相环电路进行了流片验证，达到课题预期目标。