适用于无线传感器网络SOC的低功耗低成本SAR型A/D转换器设计研究

A wireless sensor network (WSN) is a self-organized network consists of large amount of tiny sensors to monitor physical or environmental conditions. These tiny sensor nodes are able to sense, data process, and communicate. ADC is a key module of a WSN node. From the requirements for the WSN SOC, the target specification for the ADC is very tough. Designing a low power low cost ADC is always challenging with the development of the Nano-meter scaled CMOS technology. From the power efficiency and area efficiency point of view, this project develops a novel architecture for ADC design, which use a threshold configurable comparator and a split C-DAC array. Based on this, the area of C-DAC is able to effectively shrink since the dependence on the number of bit of the ADC can be relaxed. Therefore, it can dramaticlly lower the system cost and power as well. Since the WSNs are always applied in a sophisticated environment, the PVT change will degrade the linearity performance of the ADC. This project develops a on chip digital background calibration technique by detecting the density of the error codes from the ADC output. The algorithem is simple, easy for SOC and it's hardware consumes a small amount of power. The achievements of this project are expected to be widely used in many applications, such as military reconnaissance, medical detection, internet of things (IOT), and so on. In addition, the implementation of the IP core will bring profound economic benefits for the industry.

无线传感器网络（WSN）是一种以感知环境为目的、由大量具有传感、数据处理、无线通信等功能的微节点构成的自组织网络系统。WSN的SOC硬件实现对其关键模块ADC性能指标提出苛刻要求，纳米尺度集成电路的发展趋势让低功耗低成本ADC的设计面临巨大挑战。本项目将从优化ADC芯片面积和功耗角度出发，将开发一种基于阈值可调比较器和分列电容阵列DAC的新颖的SAR型ADC结构设计方法，并对其中的关键模块进行优化，由此可有效减少ADC精度对电容阵列DAC的位数的依赖，减小了DAC的面积，从而大幅降低了ADC的成本和功耗。由于WSN工作于复杂环境，PVT变化将严重影响ADC的整体性能，本项目将开发一种基于ADC误码密度分布检测的片上后向数字校正方法，其算法简单直观，易于SOC实现，且不会显著增加功耗。项目成果在军事侦察、医疗检测，物联网等领域有广泛的应用前景，其IP核的开发可带来良好的经济效益。

无线传感器网络（WSN） 的SOC 硬件实现对其关键模块ADC性能指标提出苛刻要求，纳米尺度集成电路的发展趋势让低功耗低成本ADC 的设计面临巨大挑战。本项目从优化ADC 芯片面积和功耗角度出发，开发了一种基于阈值可调比较器和分列电容阵列DAC 的新颖的SAR 型ADC 结构设计方法，并对其中的关键模块进行优化，由此可有效减少ADC 精度对电容阵列DAC 的位数的依赖，减小了DAC 的面积，从而大幅降低了ADC的成本和功耗。由于WSN 工作于复杂环境，PVT 变化将严重影响ADC 的整体性能，本项目开发了两种基于ADC 误码密度分布检测的片上后向数字校正方法，其算法简单直观，易于SOC实现，且消耗较低功耗。项目取得了以下成果:(1)完成了一款基于180nm CMOS工艺6-bit阈值可调比较器的设计并进行了流片，在此基础上完成了基于阈值比较器的6-bit 10MHz/S SAR ADC的设计，供电电压为1.2V时，其INL为0.35LSB，DNL为0.3LSB，功耗为34.5µW；（2）设计并流片了一款基于180nm CMOS工艺的具有数字后端校正功能的9位，50MHz采样率的电容分段式SAR ADC，DNL和INL分别为+0.17/-0.67 LSB和+0.65/-0.57 LSB，SNDR为52 dB。电源电压为1.8V时功耗为2.7mA；(3)设计完成了一款基于SMIC 65nm CMOS工艺，具数字有后向校正功能的，采样率为100MS/s的9-bit SAR ADC，其INL为0.15LSB，DNL为0.1LSB，校正模块的芯片面积和芯片功耗分别为0.03 mm ×0.03 mm和6.95 μW；（4）设计完成了一款12bit，采样速度200Ks/s 的全差分电容分段式SAR ADC，DNL和INL分别为+1/-0.2 LSB和+0.79/-0.92 LSB，SNDR为68.33 dB，芯片消耗电流21.6 uA。（5）设计并流片了一款基于180nm CMOS工艺的三维叠层芯片间无线能量传输系统芯片，当工作频率为1GHz、负载为130Ω时，输出电压能达到1.4V，输出电流达到11.7mA，接收功率达到了16.38mW。以上项目成果在军事侦察、医疗检测，物联网等领域有广泛的应用前景，其IP核的开发将带来良好的经济效益。