面向闪速存储系统的编译码技术研究

Multi-Level Cell (MLC) technique can be used to increase the data storage density/capacity of NAND flash memories. However, as the size of CMOS chip package scales down, flash memory also faces severe reliability challenges and cannot meet the demands for future storage systems. The objectives of this project are to investigate the error-control coding and decoding theories for flash memory storage systems, and design encoding and decoding schemes of codes for the rank modulation scheme which protect against transposition errors, which are brought by sudden and steep drops in the charge of one group of flash memory cells, and limited-magnitude errors. .The contents of this project are summarized as follows: .(1) By making a theoretical analysis of efficient strategies of interleaving permutations, we design the encoding schemes of the error-control codes based on rank modulation for transposition errors which are brought by sudden and steep drops in the charge of one group of flash memory cells. .(2) Based on permutation group theory, some efficient selection methods of subgroup codes are explored in order to design construction methods of codes for the rank modulation scheme which protect against limited-magnitude errors..(3) By building LP decoding models of the error-control codes for rank modulation, we design the LP decoding schemes of the error-control codes based on rank modulation for these two kinds of errors: transposition errors, which are brought by sudden and steep drops in the charge of one group of flash memory cells, and limited-magnitude errors..(4) The better calculation methods of soft-decision log-likelihood ratio (LLR) information for LDPC decoding are studied by optimizing the mutual information between the input and output of the multiple-read channel. Using the LLR information obtained, we design soft-decision LDPC decoding algorithms with low decoding complexity for MLC flash memory. .It is expected that new theories and methods obtained in the research of this project will provide practical error-control coding schemes for future storage systems.

多级存储单元(MLC)技术可用来提高NAND闪存的数据存储密度(容量)，然而，随着NAND闪存芯片封装尺寸的缩小，MLC型NAND闪存的可靠性面临着严峻的挑战，无法满足未来数据存储系统的需求。本项目拟研究闪存系统的差错控制编码和译码理论及方法，设计可纠 "大量电荷突发泄漏"和"强度有限"等闪存错误的纠错码编译码方案。具体内容包括：理论分析和确定有效的交织置换策略，设计纠"大量电荷突发泄漏错误"的等级调制纠错码编码方案；基于置换群论，探索良好距离特性子群码的有效选择方法，设计强度有限错误的等级调制纠错码有效构造方法；建立等级调制纠错码的LP译码模型，设计纠这两种闪存错误的相应纠错码LP译码算法；基于读信道互信息优化方法，研究LDPC码译码器对数似然比信息的有效计算方法，设计MLC型闪存LDPC码的低复杂度软判决译码算法。通过本项目的研究，期望能够为未来存储系统提供高效实用的差错控制编码方案。

随着NAND闪存芯片封装尺寸的缩小，MLC型NAND闪存的可靠性面临着严峻的挑战，无法满足未来数据存储系统的需求。基于置换码交织技术，提出了一种可以纠单个闪存单元等级移位错误的等级调制纠错码的构造方法及其译码方法，计算实例验证了所提出译码方法的正确性；同时，针对插入、删除和替换错误，研究了Davey-MacKay构造在IDS-AWGN信道下的软判决译码和硬判决译码算法。其次，提出了通过消除小瞬子来抑制二元对称信道下线性规划译码时非正则LDPC码分数伪码字的方法以及搜索规则LDPC码线性规划译码小瞬子的算法。然后，提出并证明了LDPC码线性规划译码校验节点最优分解方式；通过降低耗时的投影操作次数，提出了基于ADMM的低复杂度线性规划迭代译码算法；提出了一个降低ADMM惩罚译码器下LDPC码错误平层的两步译码方案；通过利用差分进化的方法优化权重因子，提出了基于惩罚因子的ADMM译码方法，有效改善了ADMM线性规划译码的性能；设计了LDPC码ADMM译码算法的两种改进的罚函数, 改善了LDPC码低信噪比区域的译码性能，提高LDPC码的译码速度；借助逐点消息调度策略，提出了降低LDPC码ADMM译码复杂度的方法；通过理论分析和实验比较，分析了基于加速ADMM和基于超松弛ADMM的LDPC码线性规划译码算法的高度相似性，这就表明通过组合LDPC码的这两种译码算法来提高译码速度是不可能的。最后，在深入分析现有MLC闪存信道模型及单元内部数据存储信道错误规律的基础上，设计了MLC闪存的比特翻转规则，提出了一种适用于MLC闪速存储系统的比特翻转译码算法，获得了较好的译码性能，达到了译码性能、译码复杂性和译码时间之间更好折衷；同时，提出了LDPC码有限字母表迭代译码算法及混合译码算法，有效降低了LDPC码的译码时间。本项目所取得的这些研究成果为未来存储系统提供高效实用的差错控制编码方案。